PRESENTASI

Sistem komputer
Sistem adalah Suatu kesatuan elemen yang saling berhubungan sehingga membentuk suatu kelompok dalam melaksanakan suatu tujuan pokok yang ditargetkan.Sistem komputer adalah elemen-elemen yang terkait untuk menjalankan suatu aktifitas dengan menggunakan komputer.Tujuan pokok dari sistem komputer adalah untuk mengolah data menjadi informasi.
Klasifikasi komputer
Klasifikasi Komputer dibagi dalam beberapa klasifikasi yaitu berdasarkan :
1. Jenis data yang diolah
2. Kemampuan Komputer
3. Ukuran fisik
4. Bidang Masalah


Klasifikasi komputer 1
Berdasarkan Jenis Data yang Diolah

a. Komputer Analog (Analog Computer)digunakan untuk mengolah data kualitatif
b. Komputer Digital (Digital Computer)digunakan untuk mengolah data kuantitatif
c. Komputer Hybrid (Hybrid Computer)Kombinasi komputer analog dan komputer digital



Klasifikasi komputer 2
Berdasarkan Kemampuan Komputer

• Small Scale Computer
• Medium Scale Computer
• Large Scale Computer

Berdasarkan Ukuran Fisik

• Komputer Mini (Mini Computer)
• Komputer Mikro (Micro Computer



Klasifikasi komputer 3
Berdasarkan Bidang Masalah
• Special Purpose Computer
• General Purpose Computer
Konfigurasi komputer
Komputer terbagi menjadi 3 bagian :

Hardware (Perangkat Keras)
1. Peralatan dalam bentuk fisik yang menjalankan sistem komputer.
2. Software (Perangkat Lunak)Rangkaian prosedur dan dokumentasi program yang berfungsi menyelesaikan masalah yang dikehendaki.
3. Brainware (Perangkat pikir)Orang yang menggunakan komputer

Konfigurasi hardware
Hardware terdiri dari :
• Input Device
• ProceAss Device
• Output Device
Konfigurasi hardware 1







Konfigurasi hardware 2
Keterangan gambar diatas :

CU (Control Unit)
Digunakan untuk mengatur dan menjalankan instruksi dalam urutan yang telah ditetapkan.
ALU(Arithmatic and Logic Unit)
Bagian perangkat keras yang berhubungan langsung dengan perhitungan arithmatic.
RAM (Random Access Memory)
Memori yang membaca dan menulis.
ROM (Read Only Memory)
Memori yang dapat membaca saja.

Konfigurasi hardware 3
Jenis-jenis RAM :
• SRAM ( Static RAM)
• DRAM ( Dinamic RAM)
• NVRAM
• FRAM ( Ferroeletric RAM)

Jenis-jenis ROM
• PROM ( Programmable ROM)
• EPROM (Eraseble ROM)
• EEEPROM (Electrically Eraseble Programable ROM

Konfigurasi hardware 4

Control Unit
Merupakan salah satu bagian dari sebuah CPU yang berfungsi untuk mengontrol dari data atau instruksi
Konfigurasi hardware 5
Arithmatic and Logic Unit



Memory, CU, ALU dihubungkan oleh Bus. BUS dibedakan menjadi 3 fungsi , yaitu :
1. Control BUS
2. Address BUS
3. Data BUS

Konfigurasi software
Klasifikasi Software terbagi menjadi :
Sistem Operasi (Operating Software)
perangkat lunak yang dihubungkan dengan pelaksanaan program dan koordinasi dari aktivitas sistem komputer.
Bahasa Pemrograman
bahasa komputer yang digunakab untuk menulis instruksi-instruksi program untuk melakukan suatu pekerjaan yang dilakukan oleh programer.
Program Paket
program komputer yang siap digunakan atau disebut juga program siap pakai.
Konfigurasi software(1)
Sistem Operasi (Operating System)

Fungsi dasar :
a) Menjadwalkan Tugas
b) Mengelola Sumberdaya perangkat lunak dan perangkat keras
c) Menjaga keamanan sistem
d) Memungkinkan pembagian sumberdaya untuk beberapa pemakai
e) Menyimpan catatan pemakai
f) Menangani interrupt
Konfigurasi software(2)
Bahasa Pemrograman

Adapun bahasa pemrograman yang dikenal saat ini:
1. Bahasa tingkat rendah (Low Level Language)
contoh : bahasa mesin dan bahasa rakitan
2. Bahasa tingkat menengah (Middle Level Language)
contoh : bahasa c
3. Bahasa tingkat tinggi ( High Level Language)
contoh : BASIC, COBOL, PASCAL, PL/I, ALGOL


Konfigurasi software(3)
Program Paket
Yaitu: program komputer yang siap digunakan atau diseut juga program siap pakai. Program paket digunakan untuk aplikasi bisnis secara umum, aplikasi khusus dibidang industri, aplikasi untuk meningkatkan produktifitas organisasi ayau perusahaan dan aplikasi untuk produktifitas perorangan.
Contoh : lotus 123, Dbase, dan Wordstar.
Konfigurasi brainware
Brainware dikelompokkan menjadi 3, yaitu:
Operator
seseorang yang mengoperasikan mesin komputer atau dapat pula dikatakan dengan seseorang yang menjelaskan tindakan untuk dilaksanakan.
Programer
seseorang yang bertugas merancang, menulis, dan menguji komputer
System Analyst
seseorang yang bertugas untuk melakukan spesifikasi penyelesaian masalah.
Peralatan sistem komputer
Peralatan Input
a. Keyboard
b. Mouse
c. Joystick
d. Scanner
e. Lightpen
f. Trackball
g. Touch Sreen
h. Magnetic Ink Character Reader (MICR)
i. Optical Character Reader (OCR)
j. Optical Mark Recognition (OMR) Reader
2. Perangkat Output
a. Monitor
b. Printer dan Plotter
c. Proyektor
d. microform
3. Peralatan Input / Output
a. Disk Drive
b. Tape Drive
c. Modem (Modulator Demudolator)
d. Ethernet
e. PCMCIA
f. Hub
g. Switch
h. Print Server
i. Input / Output Card (I / O Card)
j. SCII Card
k. Terminal
l. CD – Room (Compac Disk-Read Only memory)
m. CD-Read and writer
n. DVD-Room
o. DVD-Read and Writer

4. Peralatan Proses (CPU)
a. Mainboard (Motherboard)
b. I/O Card
c. SCII Card
d. VGA (Video Graphic Adapter) Card
e. Processor
f. RAM (Randon Accses Memory)
g. Catu Daya
5. Media Penyimpanan Data (Storage)
a. Floppy Disk
b. Harddisk
c. Tape
d. CD (Compact Disk)
e. DVD (Digital Video Disk)
f. Flashdisk
Monitor dapat dibagi menjadi beberpa sudut pandang :
1. Dari sudut pandang tampilan
a. Alphanumeric Display
b. Graphic display
2. Dari sudut pandang warna
a. Monochrome display
b. Color display
 CGA ( Color Display Adapter)
 EGA (Enhanced Graphic Array)
 VGA (Video Graphic Adapter)
 SVGA ( Super Video Graphic Adapter)
 XVGA

Printer dan plotter
Alat yang digunakan untuk mencetak graphic, gambar dan data lain pada selembar kertas.
Printer terbagi menjadi 3 jenis:
1. Impact printer (printer ketuk)
2. Nonimpact printer (printer tanpa ketuk)
3. Thermal printer
Perkembangan komputer
a. Perkembangan Hardware
Kemajuan tekhnologi yang dibuat manusia telah mengubah bentuk dan fun gsi komputer dalam beberapa generasi yaitu :
1. Generasi Pertama (1946 - 1959)
Masih sangat sederhana dan komplek.
Ciri – ciri :
a. Ukuran fisiknya besar
b. Kecepatan proses lambat
c. Cepat panas
d. Membutuhkan listrik besar
f. Menggunakan tabung hampa udara
g. Memorinya menggunakan core storage
h. Masih menggunakan bahasa mesin
i. Menggunakan konsep storage program.
2. Generasi Kedua (1959 - 1965)
di buat untuk menyempurnakan bentuk dari komponen .
ciri – ciri :
a. Komponen telah menggunakan transistor
b. Ukuran fisiknya lebih kecil
c. Prosesnya lebih cepat
d. Tidak cepat panas
e. Lebih hemat listrik
f. Memory yang digunakan lebih besar
g. menggunakan bahasa tingkat tinggi
3. Generasi ke tiga (1965 - 1970)
Pada generasi ini penyimpana memorynya lebih besar dan diletakkan diluar.
ciri – ciri :
a. Komponen telah menggunakan IC
b. Kecepatan prosesnya lebih cepat
c. Membutuhkan listrik lebih hemat
d. Memorynya lebih besar, dapat menyimpan sampai ribuan karakter
e. Menggunakan penyimpanan luar
f. Dapat digunakan untuk multi processing dan multi programming
g. Telah dibuat alat input output
4. Generasi keempat (1970 - 1985)
dibuat dengan menggabungkan beberapa IC yang dipadatkan. ciri – ciri :
a. Telah menggunakan LSI
b. LSI dikembangkan menjadi VLSI
c. Chip yang digunakan telah berbentuk segi empat
b. Perkembangan Software
1. Bahasa Generasi Pertama
Program yang digunakan untuk menjalankan komputer masih menggunakan bahasa mesin. Contonya. 1101011010010010 diartikan ADD
2. Bahasa Generasi KeDua
Selain bahasa mesin masih ada bahasa rakitan yang biasanya dikenal bahasa generasi kedua . Bahasa rakitan disamakan dengan bahasa tingkat rendah karena kasih dibutuhkan suatu penerjemah untuk menjalankan perintahnya
3. Bahasa Generasi Ketiga
karena pada bahasa generasi kedua masih menimbulkan kesulitan maka dibutuhkan bahasa tingkat tinggi seperti COBOL, PASCAL,BASIC, proram ini disebut dengan bahasa generasi ketiga.
4. Bahasa Generasi Keempat
pembuatan bahasa generasi keempat ditujukan untuk mamudahkan pengguna pada proses pengambilan keputusan.
5. Bahasa Generasi Kelima
bahasa generasi kelima adalah bahasa pemograman yang digunakan pada expert system. Expert System dibuat untuk memudahkan seorang programer dalam membuat sebuah program seperti layaknya seorang pakar system
komponen sistem komputer
Unit pemroses (CPU)
Main memory
Perangkat masukan dan keluaran
Interkoneksi antar komponen

Pemproses (cpu)
Unit pemroses Mengendalikan operasi komputer dan melakukan fungsi pemrosesan data, yang terdiri dari ALU, CU, Register.
Berfungsi mengendalikan operasi komputer didalam pemrosesan data, menghitung, operasi logik dan mengirim data dengan membaca instruksi dari memori dan mengeksekusi.
Main memory
Main memory berfungsi menyimpan data dan program, dan bersifat volatile.
Memori dibagi menjadi 2 :
1. Main Memory
2. Secondary memory
Organisasi sistem computer
Boot
Penyimpanan data
Register
Cache Memory
Random Access Memory
Memory Ekstensi
Direct Memory Access

SISTEM BUS DAN DMA

A. Pengertian Bus
Bus merupakan lintasan komunikasi yang menghubungkan dua atau lebih perangkat. Bus merupakan media transmisi yang dapat digunakan bersama. Sejumlah perangkat yang terhubung ke bus, dan suatu signal yang ditransmisikan oleh salah satu perangkat ini dapat diterima oleh salah satu perangkat yang terhubung ke bus. Bila dua buah perangkat melakukan transmisi dalam waktu yang bersamaa, maka signal-signalnya akan bertumpang tindih dan menjadi rusak.
Umumnya sebuah bus terdiri dari sejumlah lintasan komunikasi atau saluran. Masing-masing saluran dapat mentransimisikan signal yang menunjukkan biner 1 dan biner 0. Serangkaian digit biner dapat ditransmisikan melalui saluran tunggal. Dengan mengumpulkannya beberapa saluran dari sebuah bus dapat digunakan mentransmisikan digit biner secara bersamaan (secara paralel). Misalnya sebuah satuan data 8 bit dapat ditransmisikan melalui bus 8 saluran.
Bus terdiri dari 3:
1. Bus Data
Saluran yang memberikan lintasan bagi perpindahan data antara dua modul system. Umumnya bus data terdiri dari 8, 16, 32 saluran, jumlah saluran dikaitkan dengan lebar bus data. Karena pada suatu saat tertentu masing-masing saluran hanya dapat membawa 1 bit, maka jumlah saluran menentukan jumlah bit yang dapat diindahkan pada suatu saat. Lebar bus data merupakan factor penting dalam menentukan kinerja system secara keseluruahan. Bila bus data lebarnya 8 bit, dan setiap instruksi panjangnya 16 bit, maka CPU harus 2 kali mengakses modul memori dalam setiap siklus instruksinya.
2. Bus Alamat
Digunakan untuk menandakan sumber atau tujuan data pada bus data, misalnya CPU akan membaca sebuah word (8, 16, 32 bit) data dari memori, maka CPU akan menaruh alamat word yang dimaksud pada saluran alamat. Lebar bus alamat menentukan kapasitas memori maksimum sitem. Selain itu umumnya saluran alamt juga digunakan untuk mengalamati port-port I/O.
3. Bus Kontrol
Digunakan untuk mengontrol akses ke saluran alamat, penggunaan data dan saluran alamat. Karena data dan saluran alamat digunakan bersama oleh seluruh komponen, maka harus ada alat untuk mengontrol penggunaannya. Signal-signal kontrol melakukan transmisi baik perintah mauun informasi pewaktuan diantra modul-modul system. Signal-signal pewaktuan menunjukkan validitas data dan informasi alamat.
Umumnya saluran kontrol meliputi :
Memory Write : menyebabkan data pada bus akan dituliskan ke dalam lokasi alamat. Memory Read : menyebabkan data dari lokasi alamat ditempatkan pada bus I/O Write : menyebabkan data pada bus di output kan ke port I/O yang beralamat. I/O Read : menyebabkan data dari port I/O yang beralamat ditempatkan pada bus. Transfer ACK : menunjukkan bahwa data telah diterima dari bus atau telah ditempatkan di bus. Interrupt Request : menandakan bahwa sebuah interrupt ditangguhkan. Interrupt ACK : memberitahukan bahwa interrupt yang ditangguhkan telah diketahui. Clock : digunakan untuk mensinkronkan operasi-operasi. Reset : menginisialisasi seluruh modul.
Beberapa bus utama dalam sistem komputer modern adalah sebagai berikut:
• Bus prosesor. Bus ini merupakan bus tercepat dalam sistem dan menjadi bus inti dalam chipset dan motherboard. Bus ini utamanya digunakan oleh prosesor untuk meneruskan informasi dari prosesor ke cache atau memori utama ke chipset kontrolir memori (Northbridge, MCH, atau SPP). Bus ini juga terbagi atas beberapa macam, yakni Front-Side Bus, HyperTransport bus, dan beberapa bus lainnya. Sistem komputer selain Intel x86 mungkin memiliki bus-nya sendiri-sendiri. Bus ini berjalan pada kecepatan 100 MHz, 133 MHz, 200 MHz, 266 MHz, 400 MHz, 533 MHz, 800 MHz, 1000 MHz atau 1066 MHz. Umumnya, bus ini memiliki lebar lajur 64-bit, sehingga setiap detaknya ia mampu mentransfer 8 byte.
• Bus AGP (Accelerated Graphic Port). Bus ini merupakan bus yang didesain secara spesifik untuk kartu grafis. Bus ini berjalan pada kecepatan 66 MHz (mode AGP 1x), 133 MHz (mode AGP 2x), atau 533 MHz (mode AGP 8x) pada lebar jalur 32-bit, sehingga bandwidth maksimum yang dapat diraih adalah 2133 MByte/s. Umumnya, bus ini terkoneksi ke chipset pengatur memori (Northbridge, Intel Memory Controller Hub, atau NVIDIA nForce SPP). Sebuah sistem hanya dapat menampung satu buah bus AGP. Mulai tahun 2005, saat PCI Express mulai marak digunakan, bus AGP ditinggalkan.
• Bus PCI (Peripherals Component Interconnect). Bus PCI tidak tergantung prosesor dan berfungsi sebagai bus peripheral. Bus ini memiliki kinerja tinggi untuk sistem I/O berkecepatan tinggi. Bus ini berjalan pada kecepatan 33 MHz dengan lebar lajur 32-bit. Bus ini ditemukan pada hampir semua komputer PC yang beredar, dari mulai prosesor Intel 486 karena memang banyak kartu yang menggunakan bus ini, bahkan hingga saat ini. Bus ini dikontrol oleh chipset pengatur memori (northbridge, Intel MCH) atau Southbridge (Intel ICH, atau NVIDIA nForce MCP).
• Bus PCI Express (Peripherals Component Interconnect Express)
• Bus PCI-X (Peripherals Component Interconnect Express)
• Bus ISA (Industry Standard Architecture)
• Bus EISA (Extended Industry Standard Architecute)
• Bus MCA (Micro Channel Architecture)
• Bus SCSI (Small Computer System Interface]]. Bus ini diperkenalkan oleh Macintosh pada tahun 1984. SCSI merupakan antarmuka standar untuk drive CD-ROM, peralatan audio, harddisk, dan perangkat penyimpanan eksternal berukuran besar
• Bus USB (Universal Serial Bus). Bus ini dikembangkan oleh tujuh vendor komputer, yaitu Compaq, DEC, IBM, Intel, Microsoft, NEC, dan Northern Telecom. Bus ini ditujukan bagi perangkat yang memiliki kecepatan rendah seperti keyboard, mouse, dan printer karena tidak akan efisien jika perangkat yang berkecepatan rendah dipasang pada bus berkecepatan tinggi seperti PCI. Keuntungan yang didapat dari bus USB antara lain : tidak harus memasang jumper, tidak harus membuka casing untuk memasang peralatan I/O, hanya satu jenis kabel yang digunakan, dapat mensuplai daya pada peralatan I/O, tidak diperlukan reboot.
• Bus 1394. Bus yang mempunyai nama FireWire memiliki kecepatan tinggi diatas SCSI dan PCI. Bus 1394 sangat cepat, murah, dan mudah untuk diimplementasikan. Bus ini tidak hanya populer perangkat komputer tetapi juga perangkat elektronik seperti kamera digital, VCR, dan televisi.
A. Pengertian Sistem
Sistem adalah suatu kesatuan yang terdiri dari komponen atau elemen yang saling terhubung untuk memudahkan aliran informasi, materi atau energi.
B. Pengertian DMA
DMA adalah sebuah prosesor khusus (special purpose processor) yang berguna untuk menghindari pembebanan CPU utama oleh program I/O (PIO).


Gambar 6-2. DMA Interface.
C. Sistem Bus
Bila sebuah modul akan mengirimkan data ke modul lainnya, maka modul itu harus melakukan dua hal : 1. memperoleh penggunaan bus, dan 2 memindahkan data melalui bus. Bila sebuah modul akan meminta data dari modul lainnya, maka modul itu harus : 1. memperoleh penggunaan bus, dan 2 memindahkan sebuah request ke modul lainya melalui saluran kontrol dan saluran alamat yang sesuai. Kemudian modul harus menunggu modul kedua untuk mengirimkan data.

Bentuk fisik Bus
Bus system merupakan sejumlah konduktor listrik parallel. Konduktor-konduktor ini berupa kawat logam yang berakhir pada kartu atau papan PCB. Bus melintasi seluruh komponen system yang masing-masing disambungkan ke beberapa atau semua saluran bus.
Masalah dalam Bus Tunggal/ Single
Bila perangkat yang berjumlah sangat banyak dihubungkan ke bus, maka akan terjadi penurunan kinerja. Penyebab utama : semakin banyak perangkat yang dihubungkan ke bus, semakin besar delay propagasinya. Delay ini menentukan waktu yang diperlukan perangkat untuk mengkoordinasi pengguna bus
Bus akan menjadi tersumbat dengan semakin besarnya perpindahan data yang hampir mendekati kapasitas bus. Sampai tingkat tertentu, masalah ini dapat diatasi dengan memakai bus-bus yang lebih lebar. (misalnya meningkatkan bus data dari 32 menjadi 64 bit) Namun karena kelajuan data disebabkan oleh perangkat-perangkat yang terhubung (misalnya pengontrol grafis dan video, interface jaringan) berkembang dengan cepat maka dalam perlombaan ini besar kemungkinan bus tunggal akan menderita kekalahan.
Bus local yang menghubungkan prosesor dengan cache memory dan bus local dapat mendukung sebuah perangkat local atau lebih. Pengontrol cache memory tidak hanya menghubungkan cache dengan bus local itu saja, namun juga dengan bus system yang terhubung dengan seluruh modul memory utama. Manfaat struktur cache melindungi prosesor dari keharusan seringnya mengakses memori utama, sehingga memori utama dapat dipindahkan dari bus local ke bus sitem. Dengan cara ini, transfer I/O ke memori utama dan transfer dari memoriutama yang melintasi bus system tidak mengganggu aktivitas prosesor.
Sangat mungkin untuk menghubungkan pengontrol I/O secara langsung dengan bus system. Penyelesaian yang lebih efisien untuk masalah ini adalah dengan memanfaatkan satu bus ekspansi atau lebih. Interface bus ekspansi mem-buffer-kan transfer data antara bus system dengan pengontrol I/O pada bus ekspansi.
Contoh : Perangkat I/O yang dapat disambungkan ke bus ekspansi. Koneksi jaringan meliputi LAN misalnya koneksi Ethernet 10 Mbps dan koneksi ke WAN seperti jaringan paket switching, SCSI (Small Computer System Interface) merupakan jenis bus yang digunakan untuk mendukung disk drive local dan peripheral lainnya. Sebuah serial port dapat dipakai untuk mendukung sebuah printer atau scanner.
Arsitektur bus tradisional cukup efisien namun mulai mengalami penurunan dengan semakin tingginya kinerja pada perangkat I/O.
Untuk menjawab meningkatnya kebutuhan ini, penyelesaianya membuat bus berkecepatan tinggi yang sangat terintegrasi dengan system, yang hanya memerlukan bridge antara bus prosesor dengan bus berkecepatan tinggi.
Keuntungan pengaturan bus berkecepatan tinggi menyebabkan perangkat yang berkapasitas besar menjadi lebih terintegrasi dengan prosesor dan sekaligus tidak tergantung lagi terhadap prosesor.
Jenis-jenis Bus
Dedicated : Saluran data dan alamat terpisah
Multiplexed : Alamat dan informasi data dapat ditransmisikan melalui sejumlah saluran yang sama dengan menggunakan saluran ?Address Valid Control?. Pada awal pemindahan data, alamat ditempatkan pada bus dan ?Address Valid Control? diaktifkan. Pada saat ini setiap modul memiliki periode waktu tertentu untuk menalin alamt dan menentukan apakah alamat tersebut merupakan modul beralamat. Kemudian alamat dihapus dari bus, dan koneksi bus yang sam adigunakan untuk transfer data pembacaan atau penulisan berikutnya. Metoda penggunaan saluran yang untuk berbagai keperlua ini dikenal sebagai time multiplexing.
Keuntungan : hanya memerlukan saluran sedikit sehingga menghemat ruang dan biaya.
Kerugiannya : diperlukan rangkain yang lebih kompleks , penurunan kinerja yang cukup besar.
Bus Arbitrasi
Didalam semua system kecuali system yang paling sederhana, lebih dari satu modul diperlukan untuk mengontrol bus. Misalnya I/O mungkin diperlukan untuk membaca atau menulis secara langsung ke memori, dengan tanpa mengirimkan data ke CPU. Karena pada satu sat hanya sebuah unit yang berhasil mentransmisikan data melalui bus, maka diperlukan beberapa metode arbitrasi.
Metode Arbitrasi digolongkan sebagai metode tersentralisasi dan metode terdistribusi.
Tersentralisasi : sebuah perangkat hardware yang dikenal sebagai pengontrol bus atau arbitrer bertanggung jawab atas alokasi waktu pada bus. Mungkin perangkat berbentuk modul atau bagian CPU yang terpisah
Terdistribusi : tidak terdapat pengontrol sentral, setiap modul terdiri dari acces control logic dan modul-modul bekerja sama untuk memakai bus bersama-sama
Timing
Timing berkaitan dengan cara terjadiya event dikoordinasikan pada bus. Dengan timing yang synchronous, terjadinya event pada bus ditentukan oleh sebuah clock. Bus meliputi sebuah saluran, waktu tempat timing mentransmisikan rangkaian bilangan 1 dan 0 dalam durasi yang sama. Sebuah transmisi 1-0 dikenal sebagai siklus waktu atau siklus bus dan menentukan besarnya slot waktu. Semua perangkat lainnya pada bus dapat membaca saluran waktu, dan semua event dimulai pada awal siklus waktu.
Timing Sinkron
Signal bus lainya dapat berubah pada ujung muka signal waktu (dengan sedikit reaksi delay). Sebagian besar event mengisi suatu siklus waktu. CPU mengeluarkan signal baca dan menempatkan alamat memori pada bus alamat, CPU mengeluarkan signal awal untuk menandai keberadaan alamat dan informasi control pada bus. Modul memori mengetahui alamat itu, dan setelah delay 1 siklus menempatkan data dan signal balasan pada bus.
Timing sinkron
Terjadinya event pada bus mengikuti dan tergantung pada event sebelumnya. CPU menempatkan alamat dan membaca signal bus. Setelah berhenti untuk memberi kesempatan signal ini menjadi stabil, CPU mengeluarkan signal MSYN (master syn) yang menandakan keberadaan alamat yang valid dan signal control. Modul memori memberikan respons dengan data dan signal SSYN (slave syn) yang menunjukan respon
Timing sinkron lebih mudah untuk diimplementasikan dan ditest. Namun timing ini kurang flexible dibandingkan dengan timing asinkron. Karena semua perangkat pada bus sinkron terkait dengan kelajuan pewaktu yang tetap, maka system tidak dapat memanfaatkan peningkatan kinerja. Dengan menggunakan timing asinkron, campuran antara perangkat yang lamban dan cepat, baik dengan menggunakan teknologi lama maupun baru, dapat menggunakan bus secara bersama-sama.
Lebar Bus
Lebar bus dapat mempengaruhi kinerja system, semakin lebar bus data, semakin besar bit yang dapat ditransferkan pada suatu saat. Lebar bus alamat mempunyai pengaruh pada kapasitas system : semakin lebar bus alamat, semakin besar range lokasi yang dapat direferensi.
PCI
Pheripheral Component Interconnect (PCI) merupakan bus yang tidak tergantung prosessor berbandwidth tinggi yang dapat berfungsi sebagai bus peripheral atau bus mezzanine. PCI memberikan system yang lebih baik bagi subsistem I/O berkecepatan tinggi.. PCI dirancang untuk mendukung bermacam-macam konfigurasi berbasis microprocessor, baik system microprocessor tunggal maupun jamak. PCI memanfaatkan timing sinkron dan pola arbitrasi tersentralisasi.
PCI Saluran Bus.
Signal-signal ini dibagi menjadi kelompok-kelompok :
1. Sistem pins
Meliputi pin waktu dan reset. Address dan data : meliputi 32 saluran yang time multiplexed bagi alamat dan data. Saluran lainya untuk menginterpretasi dan mevalidasi saluran-saluran signal yang membawa alamat dan data.
2. Interface Control
Mengontrol timing transaksi dan mengkoordinasikan antara inisiator dan target.


3. Arbitration
Masing-masing master PCI memiliki pasangan saluran arbitrasinya sendiri yang menghubungkannya secara langsung dengan arbiter bus PCI.
4. Error repots
Melaporkan error parity dan eror lainnya.
5. Interupt pins
Saluran signal ini disediakan bagi perangkat-perangkat PCI yang harus menghasilkan request untuk layanan. Pin-pin ini pun bukan saluran yang dapat dipakai bersama, melainkan masing-masing PCI memilih saluran interrupt ke pengontrol interrupt.
6. Cache Support
Diperlukan untuk mendukung memori pada PCI yang dapat di cache kan di dalam prosesor 64 bit.
7. Bus Extension.
Meliputi 32 saluran yang merupakan time-multiplexed bagi alamat dan data dan dikombinasikan dengan saluran alamat/data untuk membentuk bus alamat/data 64 bit. Saluran lainnya di dalam kelompok ini digunakan untuk menginterpretasi dan memvalidasi saluran-saluran signal yang membawa alamat dan data. Terakhir terdapat dua saluran yang memungkinkan dua buah perangkat PCI untuk menyetujui penggunaan kemampuan 64 bit
8. JTAG/Boundary Scan
Saluran signal untuk pengujian prosedur-prosedur yang ditentukan dalam standard 149.1.IEEE.
D. Sistem DMA
Transfer DMA
Untuk memulai sebuah transfer DMA, host akan menuliskan sebuah DMA command block yang berisi pointer yang menunjuk ke sumber transfer, pointer yang menunjuk ke tujuan/ destinasi transfer, dan jumlah byte yang ditransfer, ke memori. CPU kemudian menuliskan alamat command block ini ke DMA controller, sehingga DMA controller dapat kemudian mengoperasikan bus memori secara langsung dengan menempatkan alamat-alamat pada bus tersebut untuk melakukan transfer tanpa bantuan CPU.
Tiga langkah dalam transfer DMA:
1. Prosesor menyiapkan DMA transfer dengan menyedia kan data-data dari device, operasi yang akan ditampilkan, alamat memori yang menjadi sumber dan tujuan data, dan banyaknya byte yang di transfer.
2. DMA controller memulai operasi (menyiapkan bus, menyediakan alamat, menulis dan membaca data), sampai seluruh blok sudah di transfer.
3. DMA controller meng-interupsi prosesor, dimana selanjutnya akan ditentukan tindakan berikutnya.
Pada dasarnya, DMA mempunyai dua metode yang berbeda dalam mentransfer data. Metode yang pertama adalah metode yang sangat baku dan simple disebut HALT, atau Burst Mode DMA, karena DMA controller memegang kontrol dari sistem bus dan mentransfer semua blok data ke atau dari memori pada single burst. Selagi transfer masih dalam progres, sistem mikroprosessor di-set idle, tidak melakukan instruksi operasi untuk menjaga internal register. Tipe operasi DMA seperti ini ada pada kebanyakan komputer.
Metode yang kedua, mengikut-sertakan DMA controller untuk memegang kontrol dari sistem bus untuk jangka waktu yang lebih pendek pada periode dimana mikroprosessor sibuk dengan operasi internal dan tidak membutuhkan akses ke sistem bus. Metode DMA ini disebut cycle stealing mode. Cycle stealing DMA lebih kompleks untuk diimplementasikan dibandingkan HALT DMA, karena DMA controller harus mempunyai kepintaran untuk merasakan waktu pada saat sistem bus terbuka.



Gambar 6-3. DMA Controller.
Handshaking
Proses handshaking antara DMA controller dan device controller dilakukan melalui sepasang kabel yang disebut DMA-request dan DMA-acknowledge. Device controller mengirimkan sinyal melalui DMA-request ketika akan mentransfer data sebanyak satu word. Hal ini kemudian akan mengakibatkan DMA controller memasukkan alamat-alamat yang dinginkan ke kabel alamat memori, dan mengirimkan sinyal melalui kabel DMA-acknowledge. Setelah sinyal melalui kabel DMA-acknowledge diterima, device controller mengirimkan data yang dimaksud dan mematikan sinyal pada DMA-request.
Hal ini berlangsung berulang-ulang sehingga disebut handshaking. Pada saat DMA controller mengambil alih memori, CPU sementara tidak dapat mengakses memori (dihalangi), walau pun masih dapat mengaksees data pada cache primer dan sekunder. Hal ini disebut cycle stealing, yang walau pun memperlambat komputasi CPU, tidak menurunkan kinerja karena memindahkan pekerjaan data transfer ke DMA controller meningkatkan performa sistem secara keseluruhan.
Cara-cara Implementasi DMA
Dalam pelaksanaannya, beberapa komputer menggunakan memori fisik untuk proses DMA , sedangkan jenis komputer lain menggunakan alamat virtual dengan melalui tahap "penerjemahan" dari alamat memori virtual menjadi alamat memori fisik, hal ini disebut direct virtual-memory address atau DVMA.
Keuntungan dari DVMA adalah dapat mendukung transfer antara dua memory mapped device tanpa intervensi CPU.
Interface Aplikasi I/O
Ketika suatu aplikasi ingin membuka data yang ada dalam suatu disk, sebenarnya aplikasi tersebut harus dapat membedakan jenis disk apa yang akan diaksesnya. Untuk mempermudah pengaksesan, sistem operasi melakukan standarisasi cara pengaksesan pada peralatan I/O. Pendekatan inilah yang dinamakan interface aplikasi I/O.
Interface aplikasi I/O melibatkan abstraksi, enkapsulasi, dan software layering. Abstraksi dilakukan dengan membagi-bagi detail peralatan-peralatan I/O ke dalam kelas-kelas yang lebih umum. Dengan adanya kelas-kelas yang umum ini, maka akan lebih mudah untuk membuat fungsi-fungsi standar (interface) untuk mengaksesnya. Lalu kemudian adanya device driver pada masing-masing peralatan I/O, berfungsi untuk enkapsulasi perbedaan-perbedaan yang ada dari masing-masing anggota kelas-kelas yang umum tadi. Device driver mengenkapsulasi tiap -tiap peralatan I/O ke dalam masing-masing 1 kelas yang umum tadi (interface standar). Tujuan dari adanya lapisan device driver ini adalah untuk menyembunyikan perbedaan-perbedaan yang ada pada device controller dari subsistem I/O pada kernel. Karena hal ini, subsistem I/O dapat bersifat independen dari hardware.
Karena subsistem I/O independen dari hardware maka hal ini akan sangat menguntungkan dari segi pengembangan hardware. Tidak perlu menunggu vendor sistem operasi untuk mengeluarkan support code untuk hardware-hardware baru yang akan dikeluarkan oleh vendor hardware.
Peralatan Block dan Karakter
Peralatan block diharapkan dapat memenuhi kebutuhan akses pada berbagai macam disk drive dan juga peralatan block lainnya. Block device diharapkan dapat memenuhi/mengerti perintah baca, tulis dan juga perintah pencarian data pada peralatan yang memiliki sifat random-access.
Keyboard adalah salah satu contoh alat yang dapat mengakses stream-karakter. System call dasar dari interface ini dapat membuat sebuah aplikasi mengerti tentang bagaimana cara untuk mengambil dan menuliskan sebuah karakter. Kemudian pada pengembangan lanjutannya, kita dapat membuat library yang dapat mengakses data/pesan per-baris.
Peralatan Jaringan
Karena adanya perbedaan dalam kinerja dan pengalamatan dari jaringan I/O, maka biasanya sistem operasi memiliki interface I/O yang berbeda dari baca, tulis dan pencarian pada disk. Salah satu yang banyak digunakan pada sistem operasi adalah interface socket.
Socket berfungsi untuk menghubungkan komputer ke jaringan. System call pada socket interface dapat memudahkan suatu aplikasi untuk membuat local socket, dan menghubungkannya ke remote socket. Dengan menghubungkan komputer ke socket, maka komunikasi antar komputer dapat dilakukan.
Jam dan Timer
Adanya jam dan timer pada hardware komputer, setidaknya memiliki tiga fungsi, memberi informasi waktu saat ini, memberi informasi lamanya waktu sebuah proses, sebagai trigger untuk suatu operasi pada suatu waktu. Fungsi fungsi ini sering digunakan oleh sistem operasi. Sayangnya, system call untuk pemanggilan fungsi ini tidak di-standarisasi antar sistem operasi Hardware yang mengukur waktu dan melakukan operasi trigger dinamakan programmable interval timer. Dia dapat di set untuk menunggu waktu tertentu dan kemudian melakukan interupsi. Contoh penerapannya ada pada scheduler, dimana dia akan melakukan interupsi yang akan memberhentikan suatu proses pada akhir dari bagian waktunya.
Sistem operasi dapat mendukung lebih dari banyak timer request daripada banyaknya jumlah hardware timer. Dengan kondisi seperti ini, maka kernel atau device driver mengatur list dari interupsi dengan urutan yang duluan datang yang duluan dilayani.
Blocking dan Nonblocking I/O
Ketika suatu aplikasi menggunakan sebuah blocking system call, eksekusi aplikasi itu akan diberhentikan untuk sementara. aplikasi tersebut akan dipindahkan ke wait queue. Dan setelah system call tersebut selesai, aplikasi tersebut dikembalikan ke run queue, sehingga pengeksekusian aplikasi tersebut akan dilanjutkan. Physical action dari peralatan I/O biasanya bersifat asynchronous. Akan tetapi, banyak sistem operasi yang bersifat blocking, hal ini terjadi karena blocking application lebih mudah dimengerti dari pada nonblocking application.
Kernel I/O Subsystem
Kernel menyediakan banyak service yang berhubungan dengan I/O. Pada bagian ini, kita akan mendeskripsikan beberapa service yang disediakan oleh kernel I/O subsystem, dan kita akan membahas bagaimana caranya membuat infrastruktur hardware dan device-driver. Service yang akan kita bahasadalah I/O scheduling, buffering, caching, spooling, reservasi device, error handling.
I/O Scheduling
Untuk menjadwalkan sebuah set permintaan I/O, kita harus menetukan urutan yang bagus untuk mengeksekusi permintaan tersebut. Scheduling dapat meningkatkan kemampuan sistem secara keseluruhan, dapat membagi device secara rata di antara proses-proses, dan dapat mengurangi waktu tunggu rata-rata untuk menyelesaikan I/O. Ini adalah contoh sederhana untuk menggambarkan definisi di atas. Jika sebuah arm disk terletak di dekat permulaan disk, dan ada tiga aplikasi yang memblokir panggilan untuk membaca untuk disk tersebut. Aplikasi 1 meminta sebuah blok dekat akhir disk, aplikasi 2 meminta blok yang dekat dengan awal, dan aplikasi 3 meminta bagian tengah dari disk. Sistem operasi dapat mengurangi jarak yang harus ditempuh oleh arm disk dengan melayani aplikasi tersebut dengan urutan 2, 3, 1.
Pengaturan urutan pekerjaan kembali dengan cara ini merupakan inti dari I/O scheduling. Sistem operasi mengembangkan implementasi scheduling dengan menetapkan antrian permintaan untuk tiap device. Ketika sebuah aplikasi meminta sebuah blocking sistem I/O, permintaan tersebut dimasukkan ke dalam antrian untuk device tersebut. Scheduler I/O mengatur urutan antrian untuk meningkatkan efisiensi dari sistem dan waktu respon rata-rata yang harus dialami oleh aplikasi. Sistem operasi juga mencoba untuk bertindak secara adil, seperti tidak ada aplikasi yang menerima service yang buruk, atau dapat seperti memberi prioritas service untuk permintaan penting yang ditunda. Contohnya, pemintaan dari subsistem mungkin akan mendapatkan prioritas lebih tinggi daripada permintaan dari aplikasi. Beberapa algoritma scheduling untuk disk I/O akan dijelaskan ada bagian Disk Scheduling.
Satu cara untuk meningkatkan efisiensi I/O subsistem dari sebuah komputer adalah dengan mengatur operasi I/O. Cara lain adalah dengan menggunakan tempat penyimpanan pada memori utama atau pada disk, melalui teknik yang disebut buffering, caching, dan spooling.
Buffering
Buffer adalah area memori yang menyimpan data ketika mereka sedang dipindahkan antara dua device atau antara device dan aplikasi. Buffering dilakukan untuk tiga buah alasan. Alasan pertama adalah untuk men-cope dengan kesalahan yang terjadi karena perbedaan kecepatan antara produsen dengan konsumen dari sebuah stream data. Sebagai contoh, sebuah file sedang diterima melalui modem dan ditujukan ke media penyimpanan di hard disk. Kecepatan modem tersebut kira-kira hanyalah 1/1000 daripada hard disk. Jadi buffer dibuat di dalam memori utama untuk mengumpulkan jumlah byte yang diterima dari modem. Ketika keseluruhan data di buffer sudah sampai, buffer tersebut dapat ditulis ke disk dengan operasi tunggal. Karena penulisan disk tidak terjadi dengan instan dan modem masih memerlukan tempat untuk menyimpan data yang berdatangan, maka dipakai 2 buah buffer. Setelah modem memenuhi buffer pertama, akan terjadi request untuk menulis di disk. Modem kemudian mulai memenuhi buffer kedua sementara buffer pertama dipakai untuk penulisan ke disk. Pada saat modem sudah memenuhi buffer kedua, penulisan ke disk dari buffer pertama seharusnya sudah selesai, jadi modem akan berganti kembali memenuhi buffer pertama dan buffer kedua dipakai untuk menulis. Metode double buffering ini membuat pasangan ganda antara produsen dan konsumen sekaligus mengurangi kebutuhan waktu di antara mereka.
Alasan kedua dari buffering adalah untuk menyesuaikan device-device yang mempunyai perbedaan dalam ukuran transfer data. Hal ini sangat umum terjadi pada jaringan komputer, dimana buffer dipakai secara luas untuk fragmentasi dan pengaturan kembali pesan-pesan yang diterima. Pada bagian pengirim, sebuah pesan yang besar akan dipecah ke paket-paket kecil. Paket-paket tersebut dikirim melalui jaringan, dan penerima akan meletakkan mereka di dalam buffer untuk disusun kembali.
Alasan ketiga untuk buffering adalah untuk mendukung copy semantics untuk aplikasi I/O. Sebuah contoh akan menjelaskan apa arti dari copy semantics. Jika ada sebuah aplikasi yang mempunyai buffer data yang ingin dituliskan ke disk. Aplikasi tersebut akan memanggil sistem penulisan, menyediakan pointer ke buffer, dan sebuah integer untuk menunjukkan ukuran bytes yang ingin ditulis. Setelah pemanggilan tersebut, apakah yang akan terjadi jika aplikasi tersebut merubah isi dari buffer, dengan copy semantics, keutuhan data yang ingin ditulis sama dengan data waktu aplikasi ini memanggil sistem untuk menulis, tidak tergantung dengan perubahan yang terjadi pada buffer. Sebuah cara sederhana untuk sistem operasi untuk menjamin copy semantics adalah membiarkan sistem penulisan untuk mengkopi data aplikasi ke dalam buffer kernel sebelum mengembalikan kontrol kepada aplikasi. Jadi penulisan ke disk dilakukan pada buffer kernel, sehingga perubahan yang terjadi pada buffer aplikasi tidak akan membawa dampak apa-apa. Mengcopy data antara buffer kernel data aplikasi merupakan sesuatu yang umum pada sistem operasi, kecuali overhead yang terjadi karena operasi ini karena clean semantics. Kita dapat memperoleh efek yang sama yang lebih efisien dengan memanfaatkan virtual-memori mapping dan proteksi copy-on-wire dengan pintar.
Caching
Sebuah cache adalah daerah memori yang cepat yang berisikan data kopian. Akses ke sebuah kopian yang di-cached lebih efisien daripada akses ke data asli. Sebagai contoh, instruksi-instruksi dari proses yang sedang dijalankan disimpan ke dalam disk, dan ter-cached di dalam memori physical, dan kemudian dicopy lagi ke dalam cache secondary and primary dari CPU. Perbedaan antara sebuah buffer dan ache adalah buffer dapat menyimpan satu-satunya informasi datanya sedangkan sebuah cache secara definisi hanya menyimpan sebuah data dari sebuah tempat untuk dapat diakses lebih cepat.
Caching dan buffering adalah dua fungsi yang berbeda, tetapi terkadang sebuah daerah memori dapat digunakan untuk keduanya. sebagai contoh, untuk menghemat copy semantics dan membuat scheduling I/O menjadi efisien, sistem operasi menggunakan buffer pada memori utama untuk menyimpan data.
Buffer ini juga digunakan sebagai cache, untuk meningkatkan efisiensi I/O untuk file yang digunakan secara bersama-sama oleh beberapa aplikasi, atau yang sedang dibaca dan ditulis secara berulang-ulang.
Ketika kernel menerima sebuah permintaan file I/O, kernel tersebut mengakses buffer cacheuntuk melihat apakah daerah memori tersebut sudah tersedia dalam memori utama. Jika iya, sebuah physical disk I/O dapat dihindari atau tidak dipakai. penulisan disk juga terakumulasi ke dalam buffer cache selama beberapa detik, jadi transfer yang besar akan dikumpulkan untuk mengefisiensikan schedule penulisan. Cara ini akan menunda penulisan untuk meningkatkan efisiensi I/O akan dibahas pada bagian Remote File Access.
Spooling dan Reservasi Device
Sebuah spool adalah sebuah buffer yang menyimpan output untuk sebuah device, seperti printer, yang tidak dapat menerima interleaved data streams. Walau pun printer hanya dapat melayani satu pekerjaan pada waktu yang sama, beberapa aplikasi dapat meminta printer untuk mencetak, tanpa harus mendapatkan hasil output mereka tercetak secara bercampur. Sistem operasi akan menyelesaikan masalah ini dengan meng-intercept semua output kepada printer. Tiap output aplikasi sudah di-spooled ke disk file yang berbeda. Ketika sebuah aplikasi selesai mengeprint, sistem spooling akan melanjutkan ke antrian berikutnya. Di dalam beberapa sistem operasi, spooling ditangani oleh sebuah sistem proses daemon. Pada sistem operasi yang lain, sistem ini ditangani oleh in-kernel thread. Pada kedua kasus, sistem operasi menyediakan interfacekontrol yang membuat users and system administrator dapat menampilkan antrian tersebut, untuk mengenyahkan antrian-antrian yang tidak diinginkan sebelum mulai di-print.
Untuk beberapa device, seperti drive tapedan printer tidak dapat me-multiplex permintaan I/O dari beberapa aplikasi. Spooling merupakan salah satu cara untuk mengatasi masalah ini. Cara lain adalah dengan membagi koordinasi untuk multiple concurrent ini. Beberapa sistem operasi menyediakan dukungan untuk akses device secara eksklusif, dengan mengalokasikan proses ke device idle dan membuang device yang sudah tidak diperlukan lagi. Sistem operasi lainnya memaksakan limit suatu file untuk menangani device ini. Banyak sistem operasi menyediakan fungsi yang membuat proses untuk menangani koordinat exclusive akses diantara mereka sendiri.
Error Handling
Sebuah sistem operasi yang menggunakan protected memory dapat menjaga banyak kemungkinan error akibat hardware mau pun aplikasi. Devices dan transfer I/O dapat gagal dalam banyak cara, bisa karena alasan transient, seperti overloaded pada network, mau pun alasan permanen yang seperti kerusakan yang terjadi pada disk controller. Sistem operasi seringkali dapat mengkompensasikan untuk kesalahan transient. Seperti, sebuah kesalahan baca pada disk akan mengakibatkan pembacaan ulang kembali dan sebuah kesalahan pengiriman pada network akan mengakibatkan pengiriman ulang apabila protokolnya diketahui. Akan tetapi untuk kesalahan permanent, sistem operasi pada umumnya tidak akan bisa mengembalikan situasi seperti semula.
Sebuah ketentuan umum, yaitu sebuah sistem I/O akan mengembalikan satu bit informasi tentang status panggilan tersebut, yang akan menandakan apakah proses tersebut berhasil atau gagal. Sistem operasi pada UNIX menggunakan integer tambahan yang dinamakan errno untuk mengembalikan kode kesalahan sekitar 1 dari 100 nilai yang mengindikasikan sebab dari kesalahan tersebut. Akan tetapi, beberapa perangkat keras dapat menyediakan informasi kesalahan yang detail, walau pun banyak sistem operasi yang tidak mendukung fasilitas ini.
Kernel Data Structure
Kernel membutuhkan informasi state tentang penggunakan komponen I/O. Kernel menggunakan banyak struktur yang mirip untuk melacak koneksi jaringan, komunikasi karakter-device, dan aktivitas I/O lainnya. UNIX menyediakan akses sistem file untuk beberapa entiti, seperti file user, raw devices, dan alamat tempat proses. Walau pun tiap entiti ini didukung sebuah operasi baca, semantics-nya berbeda untuk tiap entiti. Seperti untuk membaca file user, kernel perlu memeriksa buffer cache sebelum memutuskan apakah akan melaksanakan I/O disk.
Untuk membaca sebuah raw disk, kernel perlu untuk memastikan bahwa ukuran permintaan adalah kelipatan dari ukuran sektor disk, dan masih terdapat di dalam batas sektor. Untuk memproses citra, cukup perlu untuk mengkopi data ke dalam memori. UNIX mengkapsulasikan perbedaan-perbedaan ini di dalam struktur yang uniform dengan menggunakan teknik object oriented.
Beberapa sistem operasi bahkan menggunakan metode object oriented secara lebih extensif. Sebagai contoh, Windows NT menggunakan implementasi message-passing untuk I/O. Sebuah permintaan I/O akan dikonversikan ke sebuah pesan yang dikirim melalui kernel kepada I/O manager dan kemudian ke device driver, yang masing-masing bisa mengubah isi pesan. Untuk output, isi message adalah data yang akan ditulis. Untuk input, message berisikan buffer untuk menerima data. Pendekatan message-passing ini dapat menambah overhead, dengan perbandingan dengan teknik prosedural yang men-share struktur data, tetapi akan mensederhanakan struktur dan design dari sistem I/O tersebut dan menambah fleksibilitas.


RISC & CISC

PROSESOR RISC : Perkembangan dan Prospeknya
PROSESOR RISC :Perkembangan dan Prospeknya
Pendahuluan
Ditinjau dari perancangan perangkat instruksinya, ada dua arsitektur prosesor yang menonjol
saat ini, yakni arsitektur RISC (Reduce Instruction Set Computer) dan CISC (Complex
Instruction Set Computer).
Prosesor CISC memiliki instruksi-instruksi kompleks untuk memudahkan penulisan program
bahasa
assembly
, sedangkan prosesor RISC memiliki instruksi-instruksi sederhana yang dapat dieksekusi
dengan cepat untuk menyederhanakan implementasi rangkaian kontrol internal prosesor.
Karenanya, prosesor RISC dapat dibuat dalam luasan keping semikonduktor yang relatif lebih
sempit dengan jumlah komponen yang lebih sedikit dibanding prosesor CISC. Perbedaan
orientasi di antara kedua prosesor ini menyebabkan adanya perbedaan sistem secara
keseluruhan, termasuk juga perancangan kompilatornya.
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PROSESOR RISC : Perkembangan dan Prospeknya
Ciri-ciri Prosesor RISC
Sebenarnya, prosesor RISC tidak sekedar memiliki instruksi-instruksi yang sedikit dan
sederhana seperti namanya tetapi juga mencakup banyak ciri-ciri lain yang tidak semuanya
disepakati oleh kalangan perancang sendiri. Meskipun demikian, banyak yang telah
bersepakat bahwa prosesor memiliki ciri-ciri tertentu untuk membedakannya dengan prosesor
bukan RISC.
Pertama, prosesor RISC mengeksekusi instruksi pada setiap satu siklus detak (Robinson,
1987 : 144; Johnson, 1987 : 153). Hasil penelitihan IBM (International Business Machine) men
unjukkan bahwa frekuensi penggunaan instruksi-instruksi kompleks hasil kompilasi sangat kecil
dibanding dengan instruksi-instruksi sederhana. Dengan perancangan yang baik instruksi
sederhana dapat dibuat agar bisa dieksekusi dalam satu siklus detak. Ini tidak berarti bahwa
dengan sendirinya prosesor RISC mengeksekusi program secara lebih cepat dibanding
prosesor CISC. Analogi sederhananya adalah bahwa kecepatan putar motor
(putaran per menit)
yang makin tinggi pada kendaraan tidaklah berarti bahwa jarak yang ditempuh kendaraan
(meter per menit)
tersebut menjadi lebih jauh, karena jarak tempuh masih bergantung pada perbandingan roda
gigi yang dipakai.
Kedua, instruksi pada prosesor RISC memiliki format-tetap, sehingga rangkaian pengontrol
instruksi menjadi lebih sederhana dan ini berarti menghemat penggunaan luasan keping
semikonduktor. Bila prosesor CISC (misalnya Motorola 68000 atau Zilog Z8000)
memanfaatkan 50% - 60% dari luas keping semikonduktor untuk rangkaian pengontrolnya,
prosesor RISC hanya memerlukan 6%-10%. Eksekusi instruksi menjadi lebih cepat karena
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PROSESOR RISC : Perkembangan dan Prospeknya
rangkaian menjadi lebih sederhana (Robinson, 1987 : 144; Jonhson 1987 : 153).
Ketiga, instruksi yang berhubungan dengan memori hanya instruksi isi (load) dan instruksi
simpan (store) ,
instruksi lain dilakukan dalam register internal prosesor. Cara ini menyederhanakan mode
pengalamatan
(addressing)
dan memudahkan pengulangan kembali instruksi untuk kondisi-kondisi khusus yang
dikehendaki (Robinson, 1987 : 144; Jonhson, 1987: 153). Dengan ini pula perancang lebih
menitikberatkan implementasi lebih banyak register dalam cip prosesor. Dalam prosesor RISC,
100 buah register atau lebih adalah hal yang biasa. Manipulasi data yang terjadi pada register
yang umumnya lebih cepat daripada dalam memori menyebabkan prosesor RISC berpotensi
beroperasi lebih cepat.
Keempat, prosesor RISC memerlukan waktu kompilasi yang lebih lama daripada prosesor
RISC. Karena sedikitnya pilihan instruksi dan mode pengalamatan yang dimiliki prosesor RISC,
maka diperlukan optimalisasi perancangan kompilator agar mampu menyusun urutan
instruksi-instruksi sederhana secara efisien dan sesuai dengan bahasa pemrograman yang
dipilih. Keterkaitan desain prosesor RISC dengan bahasa pemrograman memungkinkan
dirancangnya kompilator yang dioptimasi untuk bahasa target tersebut.
3 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Fase Awal Perkembangan Prosesor RISC
Ide Dasar
Ide dasar prosesor RISC sebenarnya bisa dilacak dari apa yang disarankan oleh Von
Neumann pada tahun 1946. Von Neumann menyarankan agar rangkaian elektronik untuk
konsep logika diimplementasikan hanya bila memang diperlukan untuk melengkapi sistem agar
berfungsi atau karena frekuensi penggunaannya cukup tinggi (Heudin, 1992 : 18). Jadi ide
tentang RISC, yang pada dasarnya adalah untuk menyederhanakan realisasi perangkat keras
prosesor dengan melimpahkan sebagian besar tugas kepada perangkat lunaknya, telah ada
pada komputer elektronik pertama. Seperti halnya prosesor RISC, komputer elektronik pertama
merupakan komputer eksekusi-langsung yang memiliki instruksi sederhana dan mudah
didekode.
4 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Hal yang sama dipercayai juga oleh Seymour Cray, spesialis pembuat superkomputer. Pada
tahun 1975, berdasarkan kajian yang dilakukannya, Seymour Cray menyimpulkan bahwa
penggunaan register sebagai tempat manipulasi data menyebabkan rancangan instruksi
menjadi sangat sederhana. Ketika itu perancang prosesor lain lebih banyak membuat
instruksi-instruksi yang merujuk ke memori daripada ke register seperti rancangan Seymour
Cray. Sampai akhir tahun 1980-an komputer-komputer rancangan Seymour Cray, dalam
bentuk superkomputer seri Cray, merupakan komputer-komputer dengan kinerja sangat tinggi.
Pada tahun 1975, kelompok peneliti di IBM di bawah pimpinan George Radin, memulai
merancang komputer berdasar konsep John Cocke. Berdasarkan saran John Cocke, setelah
meneliti frekuensi pemanfaatan instruksi hasil kompilasi suatu program, untuk memperoleh
prosesor berkinerja tinggi tidak perlu diimplementasikan instruksi kompleks ke dalam prosesor
bila instruksi tersebut dapat dibuat dari instruksi-instruksi sederhana yang telah dimilikinya.
Kelompok IBM ini menghasilkan komputer 801 yang menggunakan instruksi format-tetap dan
dapat dieksekusi dalam satu siklus detak (Robinson, 1987 : 143). Komputer 801 yang dibuat
dengan teknologi ECL (emitter-coupled logic) , 32 buah register, chace terpisah untuk memori
dan instruksi ini diselesaikan pada tahun 1979. Karena sifatnya yang eksperimental, komputer
ini tidak dijual di pasaran.
Prosesor RISC Berkeley
5 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Kelompok David Patterson dari Universitas California memulai proyek RISC pada tahun 1980
dengan tujuan menghindari kecenderungan perancangan prosesor yang perangkat
instruksinya semakin kompleks sehingga memerlukan perancangan rangkaian kontrol yang
semakin rumit dari waktu ke waktu. Hipotesis yang diajukan adalah bahwa implementasi
instruksi yang kompleks ke dalam perangkat instruksi prosesor justru berdampak negatif
pemakaian instruksi tersebut dalam kebanyakan program hasil komplikasi (Heudin, 1992 : 22).
Apalagi, instruksi kompleks itu pada dasarnya dapat disusun dari instruksi-instruksi sederhana
yang telah dimiliki.
Rancangan prosesor RISC-1 ditujukan untuk mendukung bahasa C, yang dipilih karena
popularitasnya dan banyaknya pengguna. Realisasi rancangan diselesaikan oleh kelompok
Patterson dalam waktu 6 bulan. Fabrikasi dilakukan oleh MOVIS dan XEROX dengan
menggunakan teknologi silikon NMOS (N-channel Metal-oxide Semiconductor) 2 mikron.
Hasilnya adalah sebuah cip rangkaian terpadu dengan 44.500 buah transistor (Heudin, 1992 :
230). Cip RISC-1 selesai dibuat pada musim panas dengan kecepatan eksekusi 2 mikrosekon
per instruksi (pada frekuensi detak 1,5 MHz), 4 kali lebih lambat dari kecepatan yang
ditargetkan. Tidak tercapainya target itu disebabkan terjadinya sedikit kesalahan perancangan,
meskipun kemudian dapat diatasi dengan memodifikasi rancangan
assembler
nya.
Berdasarkan hasil evaluasi, meskipun hanya bekerja pada frekuensi detak 1,5 MHz dan
mengandung kesalahan perancangan, RISC-1 terbukti mampu mengeksekusi program bahasa
C lebih cepat dari beberapa prosesor CISC, yakni MC68000, Z8002, VAX-11/780, dan
PDP-11/70.
6 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Hampir bersamaan dengan proses fabrikasi RISC-1, tim Berkeley lain mulai bekerja untuk
merancang RISC-2. Cip yang dihasilkan tidak lagi mengandung kesalahan sehingga mencapai
kecepatan operasi yang ditargetkan, 330 nanosekon tiap instruksi (Heudin, 1992 : 27-28).
RISC-2 hanya memerlukan luas cip 25% dari yang dibutuhkan RISC-1 dengan 75% lebih
banyak register. Meskipun perangkat instruksi yang ditanamkan sama dengan perangkat
instruksi yang dimiliki RISC-1, tetapi di antara keduanya terdapat perbedaan mikroarsitektur
perangkat kerasnya. RISC-2 memiliki 138 buah register yang disusun sebagai 8 jendela
register, dibandingkan dengan 78 buah register yang disusun sebagai 6 jendela register. Selain
itu, juga terdapat perbedaan dalam hal organisasi alur-pipa (pipeline) . RISC-1 memiliki
alur-pipa dua tingkat sederhana dengan penjeputan
(fetch)
dan eksekusi instruksi yang dibuat tumpang-tindih, sedangkan RISC-2 memiliki 3 buah
alur-pipa yang masing-masing untuk penjemputan instruksi, pembacaan operan dan
eksekusinya, dan penulisan kembali hasilnya ke dalam register.
Sukses kedua proyek memacu tim Berkeley untuk mengerjakan proyek SOAR (Smalltalk on
RISC) yang
dimulai pada tahun 1983. Tujuan proyek ini adalah untuk menjawab pertanyaan apakah
arsitektur RISC bekerja baik dengan bahasa pemrograman Smalltalk? Jadi proyek SOAR ini
merupakan upaya pertama menggunakan pendekatan RISC untuk pemrosesan simbolik.
Versi pertama mikroprosesor SOAR diimplementasikan dengan menggunakan teknologi
NMOS 4 mikron. Cip yang dihasilkan memiliki 35.700 buah transistor dan bekerja dengan
kecepatan 300 nanosekon tiap instruksi. Versi kedua yang dirancang pada 1984-1985
menggunakan teknologi CMOS (Complementary Metal-oxide Semiconductor). Beberapa
7 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
prosesor berarsitektur RISC banyak yang dipengaruhi oleh rancangan mikroprosesor SOAR,
misalnya mikroprosesor SPARC (dari Sun Microsystems Inc.) dan KIM20 yang dirancang
Departemen Pertahanan Perancis.
Mengikuti proyek SOAR, kelompok Berkeley kemudian mengerjakan proyek SPUR (Symbolic
Processing Using RISC)
yang dimulai tahun 1985. Proyek SPUR bertujuan untuk merancang stasiun-kerja
(workstation)
multiprosesor sebagai bagian dari riset tentang pemrosesan paralel (Robinson, 1987 : 145).
Selain itu, proyek SPUR juga melakukan penelitian tentang rangkaian terpadu, arsitektur
komputer, sistem operasi, dan bahasa pemrograman. Sistem prosesor SPUR dibangun
dengan 6-12 prosesor berkinerja tinggi yang dihubungkan satu sama lain, serta dihubungkan
dengan memori dan peranti masukan/keluaran melalui Nubus yang telah dimodifikasi. Unjuk
kerja sistem diperbaiki dengan menambahkan
chace
sebesar 128 kilobyte pada tiap prosesor untuk mengurangi kepadatan lalu lintas data pada bus
dan mengefektifkan pengaksesan memori (Heudin, 1992 : 31).
Prosesor RISC Stanford
8 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Sementara proyek RISC-1 dan RISC-2 dilakukan kelompok Patterson di Universitas California,
pada tahun 1981 itu juga John Hennessy dari Universitas Stanford mengerjakan proyek MIPS
(Microprocessor without Interlocked Pipeline Stages)
. Pengalaman riset tentang optimasi kompilator digabungkan dengan teknologi perangkat keras
RISC merupakan kunci utama proyek MIPS ini. Tujuan utamanya adalah menghasilkan cip
mikroprosesor serbaguna 32-bit yang dirancang untuk mengeksekusi secara efisien kode-kode
hasil kompilasi (Heudin, 1992: 34).
Perangkat instruksi prosesor MIPS terdiri atas 31 buah instruksi yang dibagi menjadi 4
kelompok, yakni kelompok instruksi isi dan simpan, kelompok instruksi operasi aritmetika dan
logika, kelompok instruksi pengontrol, dan kelompok instruksi lain-lain. MIPS menggunakan
lima tingkat alur-pipa tanpa perangkat keras saling-kunci antar alur-pipa tersebut, sehingga
kode yang dieksekusi harus benar-benar bebas dari konflik antar alur-pipa.
Direalisasi dengan teknologi NMOS 2 mikron, prosesor MIPS yang memiliki 24.000 transistor
ini memiliki kemampuan mengeksekusi satu instruksi setiap 500 nanodetik. Karena
menggunakan lima tingkat alur-pipa bagian kontrol prosesor MIPS ini menyita luas cip dua kali
lipat dibanding dengan bagian kontrol pada prosesor RISC. MIPS memiliki 16 register
dibandingkan dengan 138 buah register pada RISC-2. Hal ini bukan masalah penting karena
MIPS memang dirancang untuk mebebankan kerumitan perangkat keras ke dalam perangkat
lunak sehingga menghasilkan perangkat keras yang jauh lebih sederhana dan lebih efisien.
Perangkat keras yang sederhana akan mempersingkat waktu perancangan, implementasi, dan
perbaikan bila terjadi kesalahan.
Sukses perancangan MIPS dilanjutkan oleh tim Stanford dengan merancang mikroprosesor
yang lebih canggih, yakni MIPS-X. Perancangan dilakukan oleh tim riset MIPS sebelumnya
9 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
ditambah 6 orang mahasiswa, dan dimulai pada musim panas tahun 1984. Rancangan MIPS-X
banyak diperbaruhi oleh MIPS dan RISC-2 dengan beberapa perbedaan utama :
- Semua instruksi MIPS-X merupakan operasi tunggal dan dieksekusi dalam satu siklus
detak
- Semua instruksi MIPS-X memiliki format tetap dengan panjang instruksi 32-bit
- MIPS-X dilengkapi pendukung koprosesor yang efisien dan sederhana
- MIPS-X dilengkapi pendukung untuk digunakan sebagai prosesor dasar dalam sistem
multiprosesor memori-bersama (shared memory)
- MIPS-X dilengkapi chace instruksi dalam-cip yang cukup besar (2 kilobyte)
- MIPS-X difabrikasi dengan teknologi CMOS 2 mikron.
10 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Sama seperti MIPS, MIPS-X merupakan prosesor dengan alur-pipa tanpa saling-kunci (interloc
k) pera
ngkat keras. Perangkat lunaknya dirancang untuk mengikuti pewaktuan instruksi agar tidak
terjadi konflik antar alur-pipa (Heudin, 1992 : 36-37).
Cip pertama yang dihasilkan bekerja baik dengan detak 16 MHz, lebih rendah dari target yang
dicanangkan setinggi 20 MHz, akibat tidak sempurnanya instruksi percabangan. Versi 25 MHz
dibuat dengan menggunakan teknologi CMOS 1,6 mikron. Ditambah dengan chace yang
diintregrasikan pada cip prosesor, MIPS-X berisi hampir 150.000 transistor di atas keping
seluas 8 x 8,5 mm (Heudin, 1992 : 38).
Arah Perkembangan Prosesor RISC
11 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Kebanyakan riset tentang prosesor RISC ditujukan untuk memperbaiki kinerja sistem komputer
secara keseluruhan. Analisis yang mendalam menunjukkan bahwa ada dua arah
perlembangan penting prosesor RISC yaitu upaya ke arah pemanfaatan teknologi proses yang
mampu menghasilkan prosesor cepat, misalnya teknologi bipolar ECL (emitter-coupled logic)
serta pemanfaatan bahan semikonduktor GaAs
(galium arsenida).
Arah lain adalah upaya untuk merancang arsitektur multiprosesor dan mengintegrasikan
unit-unit fungsional pendukung pemrosesan paralel dalam satu cip.
Cip-cip RISC galium Arsenida
Galium Arsenida dapat digunakan untuk menggantikan silikon dalam beberapa rangkaian
terpadu untuk pemakaian khusus. Keunggulan bahan GaAs dibandingkan silikon adalah
ketahanannya terhadap radiasi, dan ketahanannya terhadap panas, serta kecepatan mobilitas
elektronnya. Karena elektron dapat bergerak lebih cepat dalam bahan GaAs, maka cip yang
dibuat dengan bahan ini berpotensi untuk bekerja lebih cepat (Jonhsen, 1984 : 46; Robinson,
1990 : 251-254). Salah satu kendala pengembangan cip berbahan GaAs adalah sulitnya
penanganan bahan ini dibanding dengan bahan silikon karena perancang belum banyak
pengalaman dengan bahan GaAs. Meskipun demikian, teknologi yang dikuasai saat ini telah
memungkinkan untuk membuat rangkaian terintegrasi dengan tingkat kerapatan cukup tinggi
12 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
untuk merancang prosesor RISC.
Didorong oleh kebutuhan untuk merancang prosesor berkecepatan tinggi dan tahan terhadap
radiasi sesuai dengan spesifikasi yang dibutuhkan Departemen Pertahanan Amerika Serikat,
maka DARPA (Defense Advanced Research Projects Agency) memberikan dana kepada
Texas Instruments (TI), RCA, dan McDonnell-Douglas, untuk mengembangkan dan merancang
prosesor RISC dari bahan GaAs. Agar memiliki kinerja yang tinggi, DARPA menghendaki unit
prosesor sentral (central
processing unit
, CPU) dirancang dalam cip tunggal, seperti prosesor MIPS yang pengembangannya juga
dibiayai DARPA. Ditargetkan prosesor tersebut akan dapat dijalankan dengan detak
berfrekuensi 200 MHz. Ini berarti target kecepatan kerjanya adalah 200 MIPS
(million instructions per second
, juta instruksi per detik), karena pada prosesor RISC satu instruksi dieksekusi dalam satu
siklus detak.
Sistem yang dipilih terdiri dari seperangkat cip, yakni, CPU, FCOP (floating point coprocessor)
, MMU
(memory management unit)
dan
chace.
Agar bisa merealisasi CPU dalam satu cip, TI berupaya mengurangi rangkaian pengontrol
sebanyak mungkin untuk memberi lebih banyak tempat bagi register-register. Perangkat
instruksi dikembangkan berdasarkan simulasi statistik dan evaluasi atas prosesor RISC
Berkeley maupun MIPS Stanford. Seperti halnya MIPS, sekali program telah dikomplikasi ke
dalam perangkat instruksi inti (yakni level tengah antara perangkat-intruksi bergantung
perangkat-keras dengan bahasa pemrograman tingkat tinggi), suatu penerjemah bergantung
perangkat-keras akan mengubah kode ke dalam perangkat instruksi bahasa mesin dan
melakukan langkah-langkah optimasi. Perangkat instruksi yang dimiliki prosesor ini dibagi
menjadi tiga bagian yakni 29 buah instruksi CPU, 31 buah instruksi FCOP, serta 6 buah
instruksi MMU.
13 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Prosesor yang dihasilkan memiliki unjuk kerja nominal 200 MIPS, tetapi angka faktualnya
harus dikurangi dengan 32% akibat penyisipan instruksi NOP (no operation) dan dikurangi
32% lagi karena keterbatasan lebar ban memori. Angka faktual kinerja prosesor RISC GaAs ini
kira-kira 91 MIPS
(million instruction per second).
Pada waktu yang sama dengan pengembangan mikroprosesor RISC GaAs,
McDonnell-Douglas juga mulai mengembangkan mikroprosesor RISC berdasarkan teknologi
JFET tipe-penyambungan (enhancement-type junction field-effect transistor) DCFL (direct
coupled FET logic)
dengan bahan GaAs. Cip yang diberi nama MD484 sangat dipengaruhi oleh hasil rancangan
MIPS dari Universitas Stanford.
Karena saat itu teknologi GaAs hanya mampu mengintegrasikan transistor dalam jumlah yang
terbatas, maka hanya ditargetkan sejumlah 25.000 buah transistor dalam satu cip. Di dalam
mikroprosesor ditanamkan 32 buah register masing-masing 32-bit dengan perangkat instruksi
sangat mirip dengan yang dimiliki MIPS.
Salah satu keputusan sulit dalam perancangan adalah masalah memilih jumlah dan tipe
alur-pipa eksekusi. Penambahan jumlah alur-pipa menjadi lima atau enam dengan
penambahan tingkat alur-pipa untuk akses memori, akan memberi lebih banyak waktu
pengaksesan memori sehingga memudahkan perancangan sistem memori. Akan tetapi,
alur-pipa yang panjang akan menambah tundaan pencabangan sehingga memperlambat
waktu eksekusi. Kerugian kinerja akibat penyisipan instruksi NOP adalah 20-30% untuk
alur-pipa enam tingkat dan kira-kira setengahnya untuk alur-pipa lima tingkat relatif terhadap
alur-pipa empat tingkat. Akhirnya, kelompok McDonnell-Douglas memutuskan untuk
14 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
menggunakan empat tingkat alur-pipa. Untuk mengeksekusi operasi aritmetika floating point,
McDonnell Douglas juga merancang cip koprosesor
floating point.
Cip CPU yang selesai dibuat dan diuji pada tahun 1987, mampu mengeksekusi instruksi dalam
16,5 nanosekon dan memberikan kecepatan operasi 60 MIPS
(million instructions per second).
Proyek perancangan prosesor RISC GaAs lain dilakukan oleh RCA pada tahun 1989. Prosesor
32-bit rancangan RCA ini direncanakan diimplementasikan dengan GaAs VLSI (very large
scale integration)
. RCA mengatasi masalah yang dihadapi dalam perancangan cip GaAs ini dengan cara yang
berbeda dari yang dilakukan McDonnell Douglas maupun Texas Instruments. Berbeda dengan
kebanyakan prosesor RISC, format instruksinya tidak tunggal melainkan menggunakan format
satu dan dua kata. Rancangan RCA ini menggunakan 9 tingkat alur-pipa dengan dua periode
tak-aktif masing-masing 2 siklus tunggu, pertama berkaitan dengan penjemputan instruksi dan
kedua berkaitan dengan penjemputan operan untuk operasi
load
.
Kelompok riset di Universitas Michigan juga dilaporkan berhasil membuat prosesor RISC dari
bahan galium arsenida berkecepatan tinggi di atas cip berukuran 32-bit yang dihasilkan
diimplementasikan di atas cip berukuran 13,9 x 7,8 mm dengan 160.000 transistor. Di dalam
cip diintegrasikan bagian ALU (arithmetic and logic unit) , 32 buah register, dan 32 byte chace
instruksi. Karena kecilnya
chace
yang dimiliki, pemakai prosesor ini dapat menambahkan
chace
eksternal melalui kecepatan tinggi misalnya dengan SRAM (static random access memory)
berteknologi ECL. Cip ini bekerja baik dengan frekuensi detak 200 MHz.
15 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Ada beberapa permasalahan dalam perancangan komputer cepat dengan GaAs. Pertama,
adalah terbatasnya tingkat integrasi fungsi logika yang bisa diimplementasikan. Kedua, adalah
tingginya perbandingan antara waktu pengaksesan memori di luar cip dengan akses data di
dalam cip. SODIMA S.A. mengusulkan arsitektur 4-tingkat 32-bit untuk diintegrasikan dengan
menggunakan teknologi sel standar. Tim SODIMA juga merancang arsitektur chacechace kecil
berkecepatan tinggi (4-kilobyte dengan waktu akses 3 nanosekon) dikombinasikan dengan
chace
besar tetapi lebih lambat (128 kilobyte dengan waktu akses 25 nanosekon) untuk mendapatkan
kinerja 100 MIPS.
dua tingkat berdasarkan pada
Cip RISC lain
Advanced Micro Devices (AMD) memperkenalkan produk RISC-nya pada tahun 1987, yang
diberi nama Am29000. Dengan eksekusi siklus tunggal, prosesor yang memiliki detak
berfrekuensi 25MHz ini memiliki kecepatan proses 17 MIPS untuk program bahasa C. Ada dua
tingkat optimasi kinerja yang dilakukan dalam perancangan Am29000. Pertama, prosesor ini
memiliki jumlah register cukup banyak (192 buah) yang dapat difungsikan sebagai chace(stack
) instr
uksi saat suatu prosedur dipanggil atau sebagai kelompok register, masing-masing terdiri atas
16 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
16 buah register. Rancangan khusus dalam Am29000 adalah
chace
untuk target pencabangan yang mampu menyimpan 128 instruksi. Cara ini memungkinkan
alur-pipa tetap terisi tanpa adanya penundaan sebagai akibat dari operasi percabangan yang
berturutan (Heudin, 1992 : 104).
untuk menetapkan tumpukan
Selain AMD, Intel yang dikenal sebagai pemasok mikroprosesor CISC keluarga-86, juga
memproduksi cip mikroprosesor RISC yang diberi nama 80860 pada tahun 1989. Dengan
mengintegrasikan lebih dari sejuta transistor, 80860 berisi teras RISC (RISC core) , koprosesor
atau unit flo
ating point,
MMU
(memory management unit)
, unit grafik, dan
chace
terpisah untuk data dan instruksi. Keberadaan MMU dan teras RISC memungkinkan 80860
menjalankan sistem operasi
multitasking.
Koprosesornya mendukung aplikasi pemodelan, pengolahan suara, simulasi, dan perancangan
berbantuan komputer (Margulis, 1989 : 333). Teras RISC memiliki empat tingkat alur-pipa yang
meliputi tingkat penjemputan, dekode, eksekusi, dan penulisan instruksi. Keistimewaannya,
prosesor ini dirancang agar pemrogram dapat memilih sendiri mode eksekusi yang diperlukan,
yakni instruksi-tunggal dan instruksi-ganda. Instruksi tunggal merupakan mode eksekusi
tradisional, dengan penjemputan instruksi berturutan. Pemberian alur-pipa memungkinkan
instruksi berturutan tersebut saling tumpang-tindih sehingga beberapa instruksi berada di
beberapa tingkat alur-pipa untuk dieksekusi kapan saja. Dengan mode instruksi-ganda,
mikroprosesor 80860 menerapkan lebih dari sekedar strategi alur-pipa. Mode ini
memungkinkan dijalankannya dua instruksi sekaligus, satu untuk teras RISC dan satu untuk
koprosesor. Koprosesor atau unit
floating point
menampilkan hasil operasi setiap satu siklus detak dan memungkinkan diselesaikannya dua
operasi sekaligus, misalnya operasi penjumlahan dan perkalian. Dengan mengkombinasikan
mode instruksi-ganda dan mode operasi-ganda, pemrogram dapat melakukan tiga operasi
sekaligus setiap satu siklus detak.
17 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Cip RISC dengan detak berfrekuensi lebih dari 300 MHz dilaporkan telah dibuat oleh Digital
Equipment Corp. (DEC). Cip yang dirancang dengan teknologi bipolar ECL itu
mengimplementasikan 468.000 buah transistor dan 206.000 resistor di atas keping berukuran
15,4 x 12,6 mm. Pada kondisi terburuk, yakni dengan tegangan catu daya -5,2 volt, prosesor
ini mampu dijalankan dengan detak internal berfrekuensi 275 MHz sedangkan dalam kondisi
puncaknya (dengan tegangan catu daya -3,9 volt) dapat beroperasi pada frekuensi detak 335
MHz. Pembangkit detak eksternal memiliki frekuensi 80 MHz yang kemudian dilipatkan oleh
rangkaian PLL (phase-locked loop) menjadi 1X - 8X. Masalah besar yang timbul dengan
teknologi bipolar ECL ini adalah kebutuhan daya yang cukup besar, yakni mencapai 115 watt.
Hal ini menyebabkan timbulnya panas berlebihan dalam cip. Untuk mengatasinya, DEC
menambahkan termosifon (penghambur panas berbentuk silinder bersirip dari tembaga) di atas
kemasan cip agar suhu dalam cip terjaga tidak lebih dari 100
o
C (Bursky, 1993 : 48-50).
Prospek Arsitektur RISC di Masa Mendatang
Perkembangan menarik terjadi pada tahun 1993 ketika aliansi tiga perusahaan terkemuka,
IBM, Apple, dan Motorola memperkenalkan produk baru mereka yakni PowerPC 601, suatu
mikroprosesor RISC 64-bit yang dirancang untuk stasiun kerja (workstation) atau komputer
18 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
personal (Thompson, 1993 : 56-74). Menarik, karena kemunculan PowerPC 601 dimaksudkan
untuk memberikan alternatif bagi dominasi prosesor CISC keluarga-86 Intel dalam komputer
rumahan. Popularitas prosesor keluarga-86 didukung oleh harganya yang murah dan
banyaknya program aplikasi yang dapat dijalankan dengan prosesor ini. Untuk itu, prosesor
PowerPC dijual dengan harga yang cukup bersaing dibandingkan dengan pentium, yakni
prosesor buatan Intel mutakhir saat itu (Thompson, 1993 : 64). Perkembangan teknologi
emulasi yang memungkinkan prosesor RISC menjalankan sistem operasi yang sama dengan
prosesor CISC keluarga-86 diperkirakan akan membuat prosesor RISC, terutama PowerPC
601, banyak digunakan di dalam komputer-komputer personal (Halfhill, 1994 : 119-130).
PowerPC 601 memiliki 32 buah register serbaguna 32-bit dan 32 buah 64-bit register
floating-point.
Untuk menyimpan sementara data dan instruksi sebelum dieksekusi, PowerPC 601 memiliki
32-kilobyte
chace
untuk data dan instruksi bersama-sama. Teras PowerPC 601 terdiri dari tiga unit eksekusi
dengan alur-pipa yang independen, yakni unit pemroses bilangan bulat (IU,
integer unit
), unit
floating-point
(FPU,
floating processing unit
), dan unit pemroses operasi percabangan (BPU,
branch processing unit
) yang mampu mengeksekusi tiga instruksi sekaligus (Ryan, 1993 : 79-80).
Perkembangan menarik juga nampak dengan diadopsinya sebagian arsitektur RISC ke dalam
prosesor CISC yang dikenal dengan sebutan arsitektur hibrid CISC/RISC. Intel Corporation
mengimplementasikan arsitektur CISC/RISC ini ke dalam prosesor keluarga-86 dimulai dengan
prosesor Pentium, kemudian prosesor P6 atau Pentium Pro (Ryan, 1993 : 84 ; Halfhill, 1995:42
; Yokota, 1993 : 18-25). Beberapa produsen lain, dengan cara berbeda juga mulai mengadopsi
arsitektur campuran CISC/RISC ini misalnya Matsushita Corp dengan prosesor V810,
Advanced RISC Machines dengan ARM610, dan Hitachi dengan prosesor SH7032 (Miyazaki,
1993 : 20-27).
19 / 20
PROSESOR RISC : Perkembangan dan Prospeknya
Kesimpulan
Prosesor RISC, yang berkembang dari riset akademis telah menjadi prosesor komersial yang
terbukti mampu beroperasi lebih cepat dengan penggunaan luas cip yang efisien. Kemajuan
mutakhir yang ditunjukkan oleh mikroprosesor PowerPC 601 dan teknologi emulasi yang
antara lain dikembangkan oleh IBM memungkinkan bergesernya dominasi cip-cip keluarga-86
dan kompatibelnya. Bila teknik emulasi terus dikembangkan maka pemakai tidak perlu lagi
mempedulikan prosesor apa yang ada di dalam sistem komputernya, selama prosesor tersebut
dapat menjalankan sistem operasi ataupun program aplikasi yang diinginkan.
20 / 20
Reduced Instruction Set Computer (RISC)
Beberapa elemen penting pada arsitektur RISC :
�� Set instruksi yang terbatas dan sederhana
�� Register general-purpose yang berjumlah banyak, atau penggunaan teknologi kompiler untuk mengoptimalkan pemakaian registernya.
�� Penekanan pada pengoptimalan pipeline instruksi.

Ditinjau dari jenis set instruksinya, ada 2 jenis arsitektur komputer, yaitu:
1. Arsitektur komputer dengan kumpulan perintah yang rumit

(Complex Instruction Set Computer = CISC)
2. Arsitektur komputer dengan kumpulan perintah yang sederhana

(Reduced Instruction Set Computer = RISC)
�� CISC dimaksudkan untuk meminimumkan jumlah perintah yang diperlukan untuk mengerjakan pekerjaan yang diberikan. (Jumlah perintah sedikit tetapi rumit)

Konsep CISC menjadikan mesin mudah untuk diprogram dalam bahasa rakitan, tetapi konsep ini menyulitkan dalam penyusunan kompiler bahasa pemrograman tingkat tinggi.
Dalam CISC banyak terdapat perintah bahasa mesin.
�� RISC menyederhanakan rumusan perintah sehingga lebih efisien dalam penyusunan kompiler yang pada akhirnya dapat memaksimumkan kinerja program yang ditulis dalam bahasa tingkat tinggi.

Konsep arsitektur RISC banyak menerapkan proses eksekusi pipeline.
Meskipun jumlah perintah tunggal yang diperlukan untuk melakukan pekerjaan yang diberikan mungkin lebih besar, eksekusi secara pipeline memerlukan waktu yang lebih singkat daripada waktu untuk melakukan pekerjaan yang sama dengan menggunakan perintah yang lebih rumit.
Mesin RISC memerlukan memori yang lebih besar untuk mengakomodasi program yang lebih besar.
IBM 801 adalah prosesor komersial pertama yang menggunakan pendekatan RISC.
Drs. Ign. Djoko Irianto, M.Eng. Revsis : 002003 Pengantar Arsitektur Komputer ArKom 03 (RISC dan CISC) PDF 3 / 2 - 8 Lebih lanjut untuk memahami RISC, diawali dengan tinjauan singkat tentang karakteristik eksekusi instruksi.
Aspek komputasi yang ditinjau dalam merancang mesin RISC adalah sbb.:
�� Operasi-operasi yang dilakukan:

Hal ini menentukan fungsi-fungsi yang akan dilakukan oleh CPU dan interaksinya dengan memori.
�� Operand-operand yang digunakan:

Jenis-jenis operand dan frekuensi pemakaiannya akan menentukan organisasi memori untuk menyimpannya dan mode pengalamatan untuk mengaksesnya.
�� Pengurutan eksekusi:

Hal ini akan menentukan kontrol dan organisasi pipeline.


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MATERI-MATERI ORKOM

PERTEMUAN 1

1
CENTRAL PROCESSOR UNIT
ARSITEKTUR KOMPUTER
Sampai saat ini komputer sudah mengalami perubahan dari model awalnya,
walaupun begitu semua komputer memiliki arsitektur dasar yang sama. Skema komputer
(computer schema), adalah diagram yang menggambarkan unit-unit dasar yang terdapat
dalam semua sistem komputer.
Gambar 1. skema komputer
1. Central processing unit (CPU), yang mengendalikan semua unit sistem komputer
yang lain dan mengubah input menjadi output.
• Primary storage (penyimpanan primer), berisi data yang sedang diolah
dan program.
• Control unit (unit pengendali), membuat semua unit bekerja sama sebagai
suatu sistem
• Arithmatika and logical Unit , tempat berlangsungkan operasi
perhitungan matematika dan logika.
2. Unit Input, memasukkan data ke dalam primary storage.
3. Secondary storage (penyimpanan sekunder), menyedikan tempat untuk
menyimpan program dan data saat tiak digunakan.
4. Unit Output, mencatat hasil pengolahan.
I. Peralatan Input
Beberapa alat input memiliki fungsi ganda, yaitu sebagai alat input dan juga
sebagai alat output untuk menghasilkan data. Alat input/ouput demikian dikenal dengan
terminal. Alat input dibagi ke dalam dua golongan yaitu alat input langsung dan tidak
langsung. Bila terminal dihubungkan dengan pusat komputer yang letaknya jauh dari
terminal melalui alat komunikasi, maka disebut dengan nama Remote Job Entry (RJE)
terminal atau Remote Batch terminal.
Control unit
Aritmathic
logical unit
primary
storage
Data input Data output
Secondary
storage
2
Alat input langsung memungkinkan input diproses secara langsung oleh CPU
melalui alat input tanpa terlebih dahulu dinmasukkan ke dalam media penyimpanan
ekternal. Alat input langsung terdiri dari beberapa golongan yaitu: keyboard, pointing
device, scanner, voice recognizer.
Alat input tidak langsung , dimana data yang dimasukkan tidak langsung diproses
oleh CPU, tetapi direkam terlebih dahulu ke suatu media mechine readable form (bentuk
yang hanya dapat dibaca oleh komputer dan merupakan penyimpanan ekternal). Alat
input tidak langsung terdiri dari: key-to-card, key-to-tape, key-to-disk.
Input hardware digunakan untuk mentranmisikan data ke processing dan storage
hardware. Peralatan yang paling popular untuk memasukkan data yaitu kombinasi antara
keyboard dan layar monitor. Layar monitor dianggap sebagai bagian dari input hardware
kerena digunakan untuk memeriksa apakah data yang akan dimasukkan telah diketik.
Disamping jenis input hardware di atas, terdapat juga input harware lainnya yaitu mouse,
scanner, voice recognition, handwriting device, machine data input (misalnya :
modem),light pen, dan bar code reader.
Voice recognition device dipakai untuk memasukkan suara manusia ke dalam
signal interpreter. Kebanyakan voice system yang digunakan sekarang mempunyai
vocabulary yang kecil dan harus dilatih untuk mengenal kata-kata tertentu. Caranya,
seseorang membacakan sebuah daftar kata-kata yang biasa digunakan sehingga signal
interpreter dapat menetapkan polanya. Misalnya pekerja menyebut box yang mereka
bawa. Voice input diperlukan karena tangan pekerja sibuk dan tidak dapat mengetik atau
memanipulasi peralatan ketik input device lainnya.
Hardwriting recognition device digunakan untuk memasukkan data dengan cara
menulis pada elektronis yang sensitive. Karakter-karakter tersebut dikenal dan
dimasukkan ke dalam system computer, biasanya suatu system PC (personal computer).
Gambar 2. Hardwriting recognition device
3
Modem merupakan salah satu jenis alat input data untuk menghubungkan
kkomputer dengan computer lain melalui jaringan telepon. Jenis input hardware lainnya
yaitu light pen yang digunakan untuk menunjuk item-item pada layar monitor dan bar
code reader yang biasa digunakan di supermarket untuk mengidentifikasi suatu jenis
barang.
Gambar 3. Modem
1. 1 Keyboard
Penciptaan keyboard komputer diilhami oleh penciptaan mesin ketik yang dasar
rancangannya di buat dan di patenkan oleh Christopere Lathan pada tahun 1868 dan
banyak dipasarkan pada tahun 1877 oleh Perusahaan Remington.
Keyboard computer pertama disesuaikan dari kartu pelunbang(punch card) dan
teknologi p[engiriman tulisan jarak jauh(teletype). Tahun 1946 komputer ENIAC
menggunakn pembaca kartu pembuat lubang(punched card reader) sebagai alat input dan
output,
Bila mendengar kata “keyboard” maka pikiran kita tidak lepas dari adanya sebuah
kompyter, karena keyboard merupakan sebuahpapan yeng terdiri dari tombol-tombol
untuk mengetikkan kalimat dan symbol-simbol khisus lainnya pada computer. Keyboard
dalam bahasa Indonesia artinya papan tombol jari atau papan tuts,
Pada keyboard terdapat tombol-tombol huruf (alphabet A-Z, a-z, angka(numeric),
0-9, tombol dan karakter khusus seperti : ` ~ @ # $ % ^ & * ( ) _ - + = / , . ? “ ‘ : ; \ |,
tombol fungsi (F1-F12), serta tobol-tobol khusus lainnya yantg jumlah seluruhnya adalah
104 tuts. Sedangkan pada mesin ketik jumlah tutsnya adalah 52 tuts. Bemtuk keyboard
umumnya persegi panjang, tetapi saat ini model keyboard sangat variatif.
Dahulu orang banyak yang menggunakan mesin ketik baik yang biasa maupun
mesin ketik listrik. Keyboard mempunyai kesamaan bentuk dan fungsi dengan mesin
ketik. Perbedaannya terletak pada hasil output atau tampilannya. Bila kita menggunakan
mesin ketik, kita tidak dapat menghapus atau membatalkan apa-apa saja yang sudah
diketikan dan setiap satu huruf atau symbol kita ketikan maka hasilnya langsung kita liat
pada kertas.tidak demikian dengan keyboard. Apa yang kita ketikan hasil atau
keluarannya dapat kita lihat dilayar monitor terlebih dahulu, kemudian kita dapat
memodifikasi atau melakukan perubahan-perubahan bentuk tulisan ,kesalahan ketikan
dan lainnya.
4
Keyboard dihubungkan ke computer dengan sebuah kabel yang terdapat pada
keyboard. Ujung kabel tersebut dimasukan kedalam port yang terdapat pada CPU
computer.
Gambar 4. Keyboard
1. 2 Mouse
Pada dasarnya, penunjuk (pointer) yang dikenal dengan sebutan”Mouse” dapat
digerakan kemana saja berdasarkan arah gerakan bola kecil yang terdapat dalam mouse.
Jika kita membuka dan mengeluarkan bola kecil yang terdapat dibelakang mouse, maka
akan terlihatdua pengendali gerak didalamnya. Kedua pengendali gerak tersebut dapat
bergerak bebas dan mengendalikan pergerakan penunjuk yang satu kearah horizontal
(mendatar) dan satu lagi Vertikal (atas dan bawah ).
Jika kita hanya menggerakan pengendali horizontal maka penunjuk hanya akan
bergrak secara horizontal saj pada layar monitor computer. Dan sebaliknya jika penunjuk
vertical yang digerakan, maka penunjuk hanya bergrak secara vertical saja dilayar
monitor.jika keduanya kita gerakan maka gerakan penunjuk (pointer) akan menjadi
diagonal. Jika bola kecil dimasukan kembali, maka bola itu akan menyentuh dan
menggerakan kedua pengendali gerak tersebut sesuai dengan arah mouse yang kita
gerakan.
Pada sebagian besar mouse terdapat tiga tombol, tetapi umumnya hanya dua
tombol yang berfungsi, yaitu tombol paling kiri dan yang paling kanan. Pengaruh dari
penekanan tombol atau yang di kenal dengan istilah “click” ini tergantung pada object
(daerah) yang kita tunjuk. Computer akan mengabaikan penekanan tombol (click) bila
tidak mengenai area atau object yang tidak penting.
Kemudian dalam penggunaan mouse juga kita kenal dengan istilah “Drag” yang
artinya menggeser atau menarik. Apabila kita menekan tombol paling kiri tanpa
melepaskannya dan sambil menggesernnya, salah satu akibatnya object tersebut
berpindah atau menjadi pindah (tersalin) ke object lain dan terdapat kemungkinan
lainnya. Kemungkinan-kemungkinan ini tergantung pada jenis program aplikasi apa yang
kita jalankan. Mouse terhubung dengan computer dengan sebuah kabel yang terdapat
pada mouse. Ujung kabel tersebut dimasukan pada port yang terdapat di CPU computer.
Gambar 5. Mouse
5
1. 3 Scanner
Scanner adalah suatu alat elektronik yang fungsinya mirip dengan mesin
foto kopi. Mesin foto kopi hasilnya dapat langsung kamu lihat pada kertas sedangkan
scanner hasilnya ditampilakn pada layar monitor computer dahulu kemudian baru dapat
dirubah dan dimodifikasi sehingga tampilan dan hasilnya menjadi bagus yang kemudian
dapat disimpan sebagai file tekx, dokuman dan gambar.
Bentuk dan ukuran scanner bermacam-macam, ada yang besarnya
seukuran dengan kertas folio, ada juga yang seukuran postcard, bahkan yang terbaru
berbentuk pena yang baru diluncurkan oleh perusahaan WizCom Technologies Inc.
scanner berukuran pena tersebut bisa menyimpan hingga 1000 halaman teks cetak dan
kemudian mentranfernya ke sebuah computer pribadi (PC). Scanner berukuran pena
tersebut dinamakan “Quicklink”. Pena scanner itu berukuran panjang enam inci dan
beratnya sekitar tiga ons. Scanner tersebut menurut WizCom dapat melakukan
pekerjaannya secara acak lebih cepat dari scanner yang berbentuk datar. Data yang telah
diambil dengan scanner itu, bisa dimasukkan secara langsung ke semua aplikasi computer
yang mengenali teks ASCII. Perbedaan tiap scanner dari merbagai merk terletak pada
pemakaian teknologi dan resolusinya. Pemakaian tekologi misalnya penggunaan tombol
digital dan teknik pencahayaan.
Gambar 6. Scaner
Cara kerja scanner :
Ketika kita menekan tombol mouse untuk memulai scanning, yang terjadi adalah :
1. penekanan tobol mouse dari computer mwnggerakan pengendali kecepatan pada
mesin scanner. Mesin yang terletak dalam scanner tersebut mengendalikan proses
pengiriman ke unit scanning
2. kemudian unit scanning menempatkan proses pengiriman ke tempat atau jalur
yang sesuai untuk langsung memulai scanning
3. nyala lampu yang telihat pada scanner menandakan bahwa kegiatan scanning
sudah mulai dilakukan
4. setelah nyala lampu sudah tidak ada, berarti proses scan sudah selesai dan
hasilnya dapat dilihat pada layar monitor
5. apabila hasil atau tampilan teks atan gambar ingin dirubah, kita dapat merubahnya
dengan menggunakn software-software aplikasi yang ada. Misalnya dengan
photoshop, adobe, pot scanned dll
6
Ada dua macam perbedaan scanner dalam memeriksa gambare yang berwarna yaitu :
1. scanner yang hanya bisa satu kali menscan warna dan menyimpan semua wara
tersebut pada saat itu saja
2. scanner yang lansung bisa tiga kali digunakan untuk menyimpan beberapa
warna. Warna-warna tersbut adalah merah, hijau, dan biru
scanner yang disebut pertama lebih cepat dibandingkan dengan yang ke dua, tetapi
menjadi kurang bagusjika digunakan reproduksi warna. Kebanyakan scanner di jalankan
pada 1 bit, 8 bit(256 warna) dan 24 bit (> 16 juta warna). Bila kita membutuhkan hasil
yang sangat baik maka dianjurkan mengunakan scanner dengan bit yang besar agar
resolusi warna lebih banyak dan bagus.
II. MEMORY SEKUNDER ( SECONDARY
MEMORY )
Memory sekunder, dipergunakan untuk menyimpan data, informasi, dan program
secara permanen sebagai berkas atau file. Contoh memory sekunder adalah floppy disk,
hard disk, zipdrive, CD-Rom, DVD, dan lain-lain. Sebagian besar memory sekunder saat
ini berbentuk disk/cakram/piringan. Operasi terhadap data, informasi, dan program
dilakukan dengan perputaran disk. Satu putaran piringan disebut RPM ( Rotation Per
Minute ). Semakin cepat perputaran, maka waktu akses akan semakin singkat. Hal ini
mengakibatkan semakin besar tekanan terhadap disk dan semakin besar panas yang
dihasilkan. Jenis memory sekunder yang akan digunakan akan menentukan kecepatan
akses dan metode akses data. Beberapa contoh ukuran kecepatan memory sekunder
adalah sebagai berikut.
• Pre-IDE : Memiliki kecepatan 3600 RPM
• IDE : Memiliki kecepatan 5200 RPM
• IDE/SCSI : Memiliki kecepatan 5400 RPM
• IDE/SCSI : Memiliki kecepatan 10000 RPM
Memory sekunder memiliki alat untuk membaca dan menulis. Alat
untukmembaca dan menulis pada harddisk disebut head sedangkan pada floppy disk
disebut side. Setiap piringan dalam disk memiliki 2 sisi head/side, yaitu sisi 0 dan sisi 1.
Head/side dibagi menjadi sejumlah lingkaran konsentrik yang disebut track. Kumpulan
track yang sama dari sebuah head yang ada disebut cylinder. Pada suatu track dibagai
menjadi daerah-daerah lebih kecil yang disebut sector. Gambaran tentang cylinder,
sector, track dsitunjukkan oleh gambar 2.8.
7
Berkas yang disimpan dalam memory sekunder dapat berinteraksi dengan
peralatan input/output dengan perantara suatu unut pengolah ( processor ).
Hubungan antara berkas dan unit input/output ditunjukkan terhadap oleh bagan dibawah
ini:
Memory sekunder mempunyai karakteristik sebagai berikut.
1. Sifat penyimpanan yang tetap ( persistent ), sehingga media penyimpanan
sekunder perlu dipisahkan dari unit pengolah utama ( central prosessing unit/
CPU ) dan memory utama ( main memory ), dan di hubungkan oleh kabel/bus ke
unit pengolah ( prosessor ) dan memory utama ( main memory )
2. Kemampuan untuk digunakan secara bersama-sama ( shareability )
3. Kemampuan untuk menyimpan sejumlah data, informasi, dan program
Langkah pengolahan data daeri dalam memory sekunder adalah sebagai berikut.
1. Menentukan lokasi data pada memory eksternal (external memory/storage )
2. Prosessor akan membaca data, dan menyalin data dari memory eksternal
( external memory/storage ) ke memory utama (main memory)
Pada saat menupdate data, maka salinan data dalam main memory yang telah
diubah akan dituliskan, yaitu dipindahkan dari main memory ke memory sekunder
Berdasarkan medianya, memory sekunder terdiri atas :
1. Optical disk
• Memnggunakan prinsip optis, yaitu berdasarkan pantulan cahaya ( sinar
laser ) pada head baca.
• Pembacaan data tidak melibatkan kontak fisik antara head dan disk
• Proses penulisan datanya lebih lambat dari pada proses pembacaan data
• Lebih awet tahan terhadap jamur, dan lain-lain
• Pembacaan data secara acak ( Random )
• Mempunyai kemampuan baca-tulis ( read/write )
• Kapasitas besar
• Ukuran kecil
• Contoh : cd rom
Berkas dalam media penyimpanan sekunder
Input device Output device
Prossesor
8
2. Magnetik storage
• Dapat terbentuk disk/tape
• Media penyimpanan ini menggunakan bahan serbuk magnet
• Akses data menggunakan prinsip induksi magnetis
• Jenis ini terdiri atas magnetic tape dan magnetic disk
2. 1 Magnetic Tape
Magnetik tape berbentuk pita panjang dan terbuat dari bahan plastic film ( mylar )
yang dapat dimagnetisasi ( ferrum oxide atau chromic oxide ) kerapatan datanta termasuk
tinggi, 1200-9000 Bpi ( bit per inchi ) sedangkan kerapatan data standar yang digunakan
adalah 800/1600 Bpi. Kecepatan pembacaan/ penulisan pada magnetic tape adalah 75-
200 inchi/det. Umumnya magnetic tape memiliki lebar pita 0.5 inchi dan memiliki
ketebalan pita 0.15 inchi ( = 3.88 mm ) atau 0.25 inchi ( 6.4 mm ) panjang pita berfariasi,
yaitu 300,600,1200 atau 2400 feet per reel.
Metode penyimpanan yang digunakan bisa dengan metode blocking ( dipisahkan
oleh interblock/ IBG ) atau tanpa bloking ( dipsahkan oleh inter record Gap/ IRG ) lebar
IRG berkisar antara 0.12-0.6 inchi sedangkan lebar IBG antar 0.3-0.75 inchi. Resiko yang
dihadapi pada media jenis ini adalah sensitive terhadap distorsi,debu, kelembaban,
magnet, dan suhu tinggi
Akses pembacaan dan penulisan data pada magnetic tape dilakukan secara
sequential dengan transfer rate relative lambat, sehingga dalam penggunaannya termasuk
media offline jumlah track pada magnetic tape bias 7/9 track. Tape 7 track digunakan
untuk tape kode bcd untuk tape dengan kode BCD, track ke 0 hingga ke 5 untuk
penulisan karakter dan track ke 6 untuk bit paritas. Sedangkan tape 9 track digunakan
untuk tape dengan kode EBCDIC ( track ke 0 hingga ke 7 untuk penulisan karakter dan
track ke 8 untuk bit paritas ) bit paritas digunakan untuk mengecek kesalahan, yang dapat
dipilih jenis odd/event check. Contoh yang termasuk dalam jenis media ini adalah pita
kaset dan real tape. Teknologi baru pada magnetic tape semakin meningkat dengan cirri
kualitas head semakin baik, data den city semakin tinggi, g a p semakin sempit
2. 2 Hard Disk
Hard disk dibuat dari bahan berupa logam yang dilapisi ferrooxide dan bahan
yang mudah termagnetisasai. Struktur hard disk tersusun atas sejumlah disk dengan
jumlah track bisa mencapai 200 track. Jumlah head pada hard disk berfariasi tergantung
jumlah disk penyusunnya. Kecepatan hard disk bisa mencapai 7500 RPM .
Hard Disk merupakan salah satu media penyimpan sekunder (storage) yang
menpunyai kapasitas yang relatife besar.program-program aplikasi berkuran besar yang
banyak beredar,mutlak memerlukan hard disk sebagai media penyimpannya.kapasitas
hard disk berfariasi mulai dari 40 MB,80 MB,640MB,840 MB,1.0GB,1.2GB,1.7 GB,2.1
GB,4,3GB,10 GB,20GB,40 GB, 60 GB, dan teknologi yang lebih baru akan memiliki
kapasitas yang semakin besar.
9
Secara garis besar,tipe harddisk ada yang berjenis SCSI dan IDE. Tipe IDE sring
disebut Fast-ATA2.tipe harddsik membedakan kecepatan transfer data, baik kecepatan
transfer prpses pembacaan atau penulisan.
Sebuah Harddisk tersusun dari komponen-komponen sebagai berikut.
1. Piringan Logam.
2. Head.
3. Rangkaian elektronik.
4. Rangkaian penguat.
5. DSP (digital signal processor)
6. Chip memory.
7. conector.
8. Spindle.
9. Actuator arm motor.
Gambar 7. Hardisk
2. 3 Removable Hardisk
Secara prinsip removable hardisk sama dengan hardisk, hanya saja dapat dipasang
dan dilepas dengan mudah. Removable hardisk dibentuk berupa cartridge, yang dipasang
pada removable rack. Removable rack tersambung pada power supplay dan kabel data
IDE interfacenya.
2. 4 Floppy Disk/Disket
Floppy disk/disk/disket secara fisik ada yang berukuran 3,5” atau 5,25”. Disk
berukuran 5,25” dibagi 2, yaitu high density yang mempunyai kapasitas 1,2MB dan
double density dengan kapasitas 360KB. Disk berukuran 3,5” ada yang memiliki
kapasitas 720KB, 1,44MB atau, 2,88MB. Akses data dalam floppy disk dilakukan dengan
menggunakan diskdrive.
Floppy disk terbuat dari bahan plastik film (mylar) yang dilapisi bahan magnetic
lentur. Susunan data dalam floppy disk diatur serial dalam track dan sector. Floppy disk
dapat mempunyai 1 indeks hole(soft sectored) atau 2 indeks hole(hard sectored).
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2. 5 Zip Drive
Zip drive meruapakan teknologi terbaru yang dikembangkan untuk mengataasi
kapasitas floppy disk. Zip drive terdiri dari atas floppy drive dan cartridge floppy khusus
yang mampu menampung data hingga hampir 100MB. Teknologi ini sangat membantu
karena ukuran data saat ini semakin besar dan seringkali tidak cukup jika disimpan dalam
floppy disk atau harus disediakan banyak floppy disk.
2. 6 CD Room
CD-Room bukanlah alat penyimpanan yang paling cepat, namun CD-Room
merupakan media pendistribusian paling murah untuk data/informasi berukuran besar.
CD-Room bukan saja digunakan untuk menyimpan data teks, tetapi juga dapat
menyimpan gambar, suara, dan animasi sehingga media ini untuk aplikasi multimedia
CD-Room merupakan salha satu media penyimpanan sekunder(storage) yang
berkapasitas besar (hingga 700MB). Banyak aplikasi yang bisa dijalankan secara
langsung dari CD-Room sehingga bisa menghemat kapasitas Hard disk. CD-Room hanya
bisa membaca data yang telah tersimpan dengan kecepatan baca data yang bervariasi,
yaitu 1x, 2x, 3x, 4x, 6x, 8x, 10x, 12x, 16x, 18x, 20x, 24x, 32x,. Saat ini kecepatan baca
tertinggi 52x.
Sekarang ini, teknologi baca-tulis untuk CD-Drive telah dimungkinkan dan sudah
banyak dipasaran. Jenis CD-Room drive adalah sebagai berikut:
1. CD-Writeable
Mampu melakukan proses baca dan tulis, tetapi proses penulisan tersebut
hanya bisa dilakukan sekali saja, data dalam CD-W ini bisa bertahan sampai
100 tahun.
2. CD-Rewriteable atau CD-Erasable
Jenis ini mampu melakukan proses baca dan tulis, dan proses tulis pada
media CD-RW dapat dilakukan berulang kali. Jadi kita bisa menghapus data
pada media tersebut dan menulisnya kembali. Data dalam CD-RW bisa
bertahan sampai 30 tahun.
2. 7 DVD (Digital Versatile Disc)
DVD merupakan kelanjutan teknologi memori sekunder menggunakan media
optical disk. DVD memiliki kapasitas hingga mencapai 9GB. Perkembangan teknologi
DVD-Room juga lebih cepat dibandingkan perkembangan teknologi CD-Room. DVDRoom
1x memungkinkan rata-rata transfer data mencapai 1.321 MB/s dengan rata-rata
Burst transfer 12MB/s. Keterangan mengenai DVD drive rate, data rate, equivalent CD
rate, serta actual CD speed ditampilkan dalam tabel 1.
DVD ada yang dapat ditulisi satu kali saja dan ada yang lebih (Recordable DVD).
Versi Recordable DVD adalah sebagai berikut:
􀂾 DVD-R for General, hanya sekali penulisan.
􀂾 DVD-R for Authoring, hanya sekali penulisan.
􀂾 DVD-RAM, dapat ditulis berulang kali.
􀂾 DVD-RW, dapat ditulis berulang kali.
􀂾 DVD+Rw, dapat ditulis berulang kali.
􀂾 DVD+R, Hanya sekali penulisan.
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DVD Drive
Speed Data Rate Equivalent CD
Rate Actual CD Speed
1x 11.08 Mbps (1.32 MB/s) 9x 8x-18x
2x 22.16 Mbps (2.64 MB/s) 18x 20x-24x
4x 44.32 Mbps (5.28 MB/s) 36x 24x-32x
5x 55.50 Mbps (6.60 MB/s) 45x 24x-32x
6x 66.48 Mbps (7.93MB/s) 54x 24x-32x
8x 88.64 Mbps (10.57 MB/s) 72x 32x-40x
10x 110.80 Mbps (13.21 MB/s) 90x 32x-40x
16x 177.28 Mbps (21.13 MB/s) 144x 32x-40x
Tabel 1
Setiap versi DVD recorder dapat membaca DVD-ROM disc, tetapi memrlukan
jenis disc yang berbeda. Jenis recorder dan jenis disc yang kompatibel terlihat pada table
2.
DVD unit DVDR(
G) unit
DVD-R(A)
unit
DVD-RW
unit
DVD-RAM
unit
DVD+RW
unit
DVDROM
Disc Reads reads Reads Reads Reads Reads
DVD-R(G)
Disc
Routinelly
reads
Reads
writes
Reads
writes Reads Reads writes Reads
DVD-R(A)
Disc
Routinelly
reads Reads Reads Reads
writes Reads Reads
DVD-RW
Disc Usually reads Reads Reads Reads
writes Usually reads Usually reads
DVDRAM
Disc Rarely reads Usually
reads
Doesn’n
reads
Doesn’t
reads Read writes Read writes
DVD+RW
Disc Usually reads Usually
reads
Usually
reads
Routinelly
reads Usually reads Read writes
DVD+
Disc
Routinelly
reads
Routinell
y reads
Routinelly
reads
Routinelly
reads
Routinelly
reads
Reads may
writes
Table 2
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2. 8 Mechanical Storage
Mechanical Storage mempunyai karakteristik sebagai berikut:
􀂾 Terbuat dari bahan semi konduktor dan unsur mekanis.
􀂾 Pembacaan dan penulisan data melibatkan unsur mekanis.
􀂾 Contoh: disket
􀂾 Unsur mekanis yang terlibat meliputi: rotasi, translasi, dan gesekan.
Unsur mekanis ini mengakibatkan kecepatan transfer datanya jauh lebih rendah
dari IC-RAM.
III. OUTPUT DEVICE
Output yang dihasilkan dari pemroses dapat digolongkan menjadi empat
bentuk,yaitu tulisan (huruf,angka,symbol khusus),image (dalam bentuk grafik atau
gambar),suara ,dan bentuk lain yang dapat dibaca oleh mesin (machine-readable
form0.Tiga golongan pertama adalah output yang dapat digunakan langsung oleh
manusia,sedangkan golongan terakhir biasanya digunakan sebagai input untuk proses
selanjutnya dari computer.
Peralatan output dapat berupa:
• Hard-copy device,yaitu alat yang digunakan untuk mencetak tulisan dan image pada
media keras seperti kertas atau film.
• Soft-copy device,yaitu alat yang digunakan untuk menampilkan tulisan dan image
pada media lunak yang berupa sinyal elektronik.
Drive device atau driver,yaitu alat yang digunakan untuk merekam symbol dalam
bentuk yang hanya dapat dibaca oleh mesin pada media seperti magnetic disk atau
magnetic tape.Alat ini berfungsi ganda,sebagai alat output dan juga sebagai alat input.
Output bentuk pertamasifatnya adalah permanen dan lebih portable (dapat dilepas
dari alat output dan dapat dibawa ke mana-mana).Alat yang umum digunakan untuk ini
adalah printer,plotter,dan alat microfilm.Sedangkan output bentuk kedua dapat berupa
video display,flat panel,dan speaker.Dan alat output bentuk ketiga yang menggunakan
media magnetic disk adalah disk driver,dan yang mengguanakn media magnetic tape
adalah tape driver.
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3. 1 Printer
Gambar 8. Printer
Klasifikasi dasar printer adalah :
a. Character printer yang mencetak satu karakter setiap kali.Contohnya yang paling
umum adalah dot matrix printer.
b. Line printer yang mencetak seluruh baris setiap kali.
c. Page printer (image printer) yang mencetak seluruh halaman setiap kali.
Metode dasar penghasilan cetakan:
a. Impact atau non-impact printing.Impact printer memukulkan atau membenturkan
pita tinta ke kertas,sedangkan non-impact printer menggunakan metode printer
lain,misalnya thermal atau elektrostatik.
b. Shaped character printing atau dot-matrix printing.Shaped character printing
mempunyai hasil cetakan yang lebih baik dari dot-matrix printing.
Kecepatan cetak (print speed):
a. Low speed (kecepatan rendah) : 10 cps / 300 lpm
Dot matrix impact character printer.Ini adalah jenis printer berkecepatan rendah
yang paling sering digunakan,dan sering disebut dengan nama “dot matrix
printer”.
Daisywheel printer.Ini adalah jenis lain printer berkecepatan rendah yang
terkenal,yang akan digunakan jika kita memerlukan kualitas cetakkan yang tinggi.
Inkjet printer.Ini adalah printer berkecepatan rendah yang tidak gaduh,karena
menggunakan cara penembakan percikan tinta yang sangat halus ke atas kertas.
b. High speed (Kecepatan tinggi) : 300 lpm – 3000 lpm
Line printer.Ini adalah impact shaped-character printer yang mencetak
keseluruhan baris setiap kalinya.
Page printer.Ini adalah printer yang mencetak tampilan sebesar halaman penuh
setiap kalinya.
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3. 2 Graph Plotter
Graph plotter digunakan untuk tujuan (penggunaan) ilmiah dan
perekayasaan.Salah satu aplikasi khususnya adalah CAD (Computer Aided
Design),dimana desain mesin atau arsitektural diciptakan oleh computer dan dikeluarkan
(outputnya pada graph plotter).
Perangkat ini memberikan bentuk output yang sama sekali berbeda,dan ia mempunyai
keragaman aplikasi.Dua jenis dasarnya adalah:
a. Flatbed type.Penanya bergerak keatas,turun,menyilang,atau menyamping.
b. Drum type.Penenya bergerak keatas,turun,dan menyilang. Kertasnya bergerak
menyamping.
Gambar 9. Garaph Plotter
3. 3 Monitor
A. PEMBAGIAN MONITOR BERDASARKAN JENIS
Pada dasarnya monitor terbagi 3 kelompok yaitu :
1. Monitor Digital
2. Monitor Analog
3. Monitor Multiscaning
1. MONITOR DIGITAL
Monitor digital adalah monitor yang menggunakan sinyal digital dalam
pengiriman data dari video card ke monitor.Sinyal digital ini adalah sinyal yang
diwakili oleh data 0 dan 1.Yang termasukan monitor jenis ini adalah monitor
Monochrome Display Adapter (MDA),Color Graphic.Adapter (CGA) dan Enhanced
Graphic Adapter (EGA).
Monitor monochrome mendukung hanya modus 7 (teks 80x25).Ukuran
characternya 9x14,jumlah scan line 350 baris dan nomor portnya 380 Hex sampai
3BB Hex.Monitor CGA diperkenalkan pada tahun 1981 (IBM PC) mendukung
modus grafik 4 warna dan modus teks 16 warna.
Jumlah scan line 200 baris,ukuran character-nya 8x8,dan nomor portnya 3D0
hex sampai 3DF Hex.Monitor EGA memiliki resolusi maksimum 640x480 dengan 2
warna.Memiliki nomor port 3C0 Hex dan jumlah scan line 350 baris sehingga dapat
menampilkan character dalam ukuran 8x14.
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2. MONITOR ANALOG
Monitor analog adalah monitor yang menggunakan sinyal analog dalam
pengiriman datanya.Sinyal analog adalah sinyal yang dapat berisi sembarang nilai
antara nilai maksimum dan minimum.Contoh monitor analog adalah Video graphic
Array Adapter (VGA)yang dikenalkan pada IBM PS/2.Nomor portnya sama dengan
EGA,scan line 400 baris sehingga dapat membentuk ukuran character 9x16.Resolusi
maksimum adalah 640x480 dengan 16 warna.
3. MONITOR MULTISCANING
Monitor multiscaning adalah monitor yang dapat menerima dua bentuk
sinyal,digital ataupun analog.Monitor ini menggabungkan kemampuan yang dimilki
monitor analog dan monitor digital,sehingga dapat dipasangkan dengan video card
yang bermacam-macam.Mendukung modus Super VGA,modus yang lebih tinggi dari
modus yang dimiliki VGA.
B. PEMBAGIAN MONITOR BERDASARKAN TEKNOLOGI
Berdasarkan teknologinya,monitor dapat dibagi atas :
1. Monitor Super VGA
2. Monitor Radiasi Rendah (Low Radiation)
3. Monitor Hemat Energi (Green Monitor)
4. Monitor Multi Fungsi
1. MONITOR SUPER VGA
Monitor Super VGA lebih baik dari VGA,memiliki dot pitch lebih kecil dari
VGA dan mendukung resolusi yang lebih tinggi.Tidak ada standar untuk monitor
Super VGA sehingga tidak jarang dijumpai 2 monitor Super VGA yang tidak sama
resolusinya.
Tidak standarnya monitor Super VGA diikuti oleh tidak standarnya video card
yang mendukung Super VGA,seperti : Tseng ET-4000,Trident,Oak Technology dan
lain-lain.Masing-masing card mempunyai nomor modus tersendiri dan tidak seragam
seperti halnya modus monochrome hingga VGA.Untuk mengatasi hal ini maka
dibuatlah standar VESA (Video Electronic Standards Association).
2. MONITOR LOW RADIATION
Tidak semua electron yang ditembakan tabung monitor dapat diserap oleh
lapisan phosphor yang terdapat pada monitor tersebut.Sebagian ada yang berhasil
lolos keluar dari monitor.Elektron yang keluar tersebut membangkitkan medan
magnet disekitar bagian depan monitor.Hal ini berbahaya bagi kesehatan
mata.Disamping umumnya jarak monitor dengan mata kurang dari 1 meter.Untuk
mencegah hal ini,dibuat monitor dengan daya magnetisasi yang kecil.Beberapa
contoh monitor low radiation adalah SPC CM-1200V Syncmaster 3,Philips
4CM2799.
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3. GREEN MONITOR
Green Monitor adalah monitor yang memiliki sifat-sifat hemat energi
pemakaian listrik dan memakai bahan-bahan yang dapat didaur ulang.Monitor
demikian dirancang dengan memakai komponen hemat listrik dan memiliki
kemampuan untuk auto-off,yang dapat mati sendiri jika setelah beberapa saat tidak
digunakan.Bahan-bahan yang digunakan membuat monitornya menggunakan bahan
yang dapat didaur ulang,terutama bahan dari plastic.
Gambar 10. Green Monitor
4. MONITOR MULTIFUNGSI
Monitor Multifungsi adalah monitor yang dapat digunakan untuk tujuan
lain,selain untuk menampilkan output dari computer,misalnya monitor yang dapat
berfungsi juga sebagai televisi,penayangan video dan lain-lain.Dewasa ini monitor
demikian banyak digunakan untuk multimedia dimana sebuah computer dapat
dihubungkan dengan berbagai macam peralatan lain seperti pengolah
data.teks,grafik,animasi,audio,dan video,CD player,sound card,laser disc dan lainlain.
C. PEMBAGIAN MONITOR BERDASARKAN ADAPTER VIDEO
Perkembangan Adapter video mulai dari yang pertama monitor monochrome dan
berlanjut dengan diciptakan adapter video untuk monitor XVGD(Extended Video
Graphics Display) hingga kini mengalami beberapa tahapan sebagai berikut :
1. Monocrome Display Adapter (MDA)
MDA merupakan suatu adapter video untuk jenis 1 warna (biasanya hijau)
dan hanya mempunyai resolusi 80 kolom x 25 baris saja,dan hanya dapat mengolah
data teks tidak dapat mengolah grafik.Di peta memori computer PC,memori MDA
terletak pada segmen B000 Hex,sebesar 4 Kb.
2. Color Graphics Adapter(CGA)
CGA dikembangkan sejak tahun 1981.CGA mendukung modus grafik dan
dapat menampilkan warna,baik pada modus teks ataupun modus grafik.Resolusi
tertinggi 640x200 baris.Di peta memori computer PC,memori CGA terletak pad
segmenB800 Hex,sebesar 16 Kb.
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3. Hercules Graphics Card (HGC)
HGC merupakan adapter video untuk jenis monitor monochrome.Adapter ini
merupakan penyempurnaan MDA,karena dapat menampilkan grafik.HGC dirancang
oleh Van Suwannukul dari Hercules Computer Technology.Resolusi tertinggi adalah
720x348 pixel.Di peta memori computer PC,letak memori HGC sama dengan untuk
MDA.
4. Enhanced Graphic Adapter (EGA)
EGA merupakan pengembangan dari CGA dengan resolusi dari tata warna
yang lebih baik.Awalnya card EGA IBM memiliki memori 64 Kb,kemudian diperluas
menjadi 128 Kb.Jadi ada 3 macam adapter card EGA.Resolusi tertinggi yang dapat
ditampilkan adalah 640xx350 pixel,Di peta memori computer PC,memori EGA
terletak pada segmen A000 Hex.
5. Profesional Graphics Adapter (PGA)
Pada saat yang sama dikeluarkan EGA,IBM memperkenalkan PGA.PGA
memiliki kemampuan untuk menampilkan grafik 3 dimensi.Adapter ini dapat
menjalankan 60 bingkai animasi per detik.Resolusi maksimumnya adalah 640x480
pixel. PGA merupakan adapter khusus untuk aplikasi CAD/CAM.Selanjutnya PGA
tidak diproduksi karena harganya mahal dan tergolong lambat.
6. Multi Color Graphics Array (MCGA)
MCGA merupakan adapter video untuk computer PS/2 model 25 dan 30.Pada
resolusi 320x200 pixel,warna yang dapat ditampilkan adalah 256 warna dari 262.144
palet warna yang tersedia.
7. Video Graphics Array (VGA)
VGA dikenalkan tahun 1987,dan sekarang menjadi standar monitor.Awalnya
VGA dibuat untuk computer PS/2,tetapi dalam perkembangan selanjutnya dapat
digunakan pada computer PC/XT dan PC/AT.Resolusi maksimumnya adalah
720x400 pixel dalam 2 warna sedangkan pada resolusi 640x480 pixel dapat
ditampilkan 256 warna.
8. Display Adapter
Adapter ini dibuat untuk PS/2 dan mempunyai resolusi yang lebih tinggi dari
VGA,dapat menampilkan 256 warna pada resolusi maksimum 1024x768 pixel pada
modus grafik,sedangkan pada modus teks dapat ditampilkan 146 kolom x 51 baris.
9. Super Video Graphic Array (SVGA)
SVGA pada dasarnya sama dengan 8514,tetapi SVGA biasa disebut pada
adapter non IBM.SVGA daoat digunakan pada PC/XT/AT,bukan untuk
PS/2.Resolusi maksimum SVGA yang umum adalah 1024x768 pixel dengan 256
warna.
18
10. Extended Graphics Adapter (XGA)
XGA merupakan adapter keluaran terakhir yang memiliki resolusi yang paling
tinggi (lebih dari 1024x768 pixel).
D. RESOLUSI DAN DOT PITCH
Resolusi adaah ukuran yang menyatakan jumlah pixel yang dapat ditampilkan di
layar.Semakin tinggi resolusi suatu monitor akan semakin halus pula gambar yang
ditampilkannya.Dotpitch adalah jarak antara 2 kesatuan phosphor merah-hijau-biru,atau
jarak antara 1 titik pixel dengan titik pixel lainnya.Dot pitch ditentukan dalam ukuran
seperseratus millimeter.
E. VERTICAL SCAN RATE (REFRESH RATE) & HORIZONTAL SCAN RATE
Refresh rate merupakan satuan berapa banyak sinaran/pancaran electron kembali
memulai dari posisi awalnya dari kiri atas monitor tiap detik.Refresh rate mempunyai 2
macam jenis,yaitu interlaced dan Non Interlaced.Pada system Interlaced,proses scaning
akan dilakukan dalam 2 kali lewatan,baris ganjil dan seterusnya.Pada umumnya system
interlaced akan menghasilkan cukup banyak flicker adalah suatu proses yang terjadi
dimana jika frekwensi penembakan electron terlalu sedikit,maka ketika penembakan
berikutnya tiba,bayangan sinar yang sebelunya masih belum hilang secara sempurna
sehingga diperoleh efek berkedip.
Horizontal scan rate dihitung dengan cara mengailkan jumlah baris perlayar dengan
besarnya refresh rate.Misal : sebuah monitor dngan resolusi 640x480 dengan refresh rate
60 Hz.maka diperlukan 28.800 scan per detik.disamping itu ada waktu yang hilang saat
antara scanning berhenti di suatu baris dan sinaran dihentikan untuk pindah ke baris
berikutnya dan proses dimulai lagi dari awal,besarnya skitar 10% sehingga secara
keseluruhan Horizontal scan raet adalah 28.800 +(28.800*10%) = 31.700 scan per detik
(31,7 KHz).Pada resolusi 800x600 dengan refresh rate 72 Hz,diperlukan monitor yang
mampu memberikan Horizontal scan rate sebesar 47,5 KHz.Pada resolusi 1042x768
dengan refresh rate 72 Hz,Horizontal scan rate yang diperlukan 59 KHz.
IV. Peranan peralatan input, output dan perangkat
lunak dalam pemecahan masalah.
Semua alat input dan output dapat berkontribusi pada pemecahan masalah baik
secara langsung dan tidak langsung. Contoh: keyboard , display, printer dan plotter
(berperan langsung), source data automation device, microfilm (berperan tidak
langsung).
Seperti halnya perangkat keras, perangkat lunak dapat juga berperan langsung
atau tidak langsung. Contoh: sistem operasi (berperan tidak langsung), aplikasi bisnis
umum dan industri (berperan tidak langsung), sebagian perangkat lunak aplikasi
peningkatan produktivitas organisasi perorangan (berperan tidak langsung), spreadsheet,
analisis statistik dan perkiraan, manajemen proyek (berperan langsung).
19
V. Sistem Operasi
Sistem operasi merupakan sebuah penghubung antara pengguna dari komputer
dengan perangkat keras komputer. Sebelum ada sistem operasi, orang hanya mengunakan
komputer dengan menggunakan sinyal analog dan sinyal digital. Seiring dengan
berkembangnya pengetahuan dan teknologi, pada saat ini terdapat berbagai sistem
operasi dengan keunggulan masing-masing. Untuk lebih memahami sistem operasi maka
sebaiknya perlu diketahui terlebih dahulu beberapa konsep dasar mengenai sistem operasi
itu sendiri.
Pengertian sistem operasi secara umum ialah pengelola seluruh sumber-daya yang
terdapat pada sistem komputer dan menyediakan sekumpulan layanan (system calls) ke
pemakai sehingga memudahkan dan menyamankan penggunaan serta pemanfaatan
sumber-daya sistem komputer.
5. 1 Fungsi Dasar
Sistem komputer pada dasarnya terdiri dari empat komponen utama, yaitu
perangkat-keras, program aplikasi, sistem-operasi, dan para pengguna. Sistem operasi
berfungsi untuk mengatur dan mengawasi penggunaan perangkat keras oleh berbagai
program aplikasi serta para pengguna.
Sistem operasi berfungsi ibarat pemerintah dalam suatu negara, dalam arti
membuat kondisi komputer agar dapat menjalankan program secara benar. Untuk
menghindari konflik yang terjadi pada saat pengguna menggunakan sumber-daya yang
sama, sistem operasi mengatur pengguna mana yang dapat mengakses suatu sumberdaya.
Sistem operasi juga sering disebut resource allocator. Satu lagi fungsi penting
sistem operasi ialah sebagai program pengendali yang bertujuan untuk menghindari
kekeliruan (error) dan penggunaan komputer yang tidak perlu.
5. 2 Tujuan Mempelajari Sistem Operasi
Tujuan mempelajari sistem operasi agar dapat merancang sendiri serta dapat
memodifikasi sistem yang telah ada sesuai dengan kebutuhan kita, agar dapat memilih
alternatif sistem operasi, memaksimalkan penggunaan sistem operasi dan agar konsep
dan teknik sistem operasi dapat diterapkan pada aplikasi-aplikasi lain.
5. 3 Sasaran Sistem Operasi
Sistem operasi mempunyai tiga sasaran utama yaitu kenyamanan -- membuat penggunaan
komputer menjadi lebih nyaman, efisien -- penggunaan sumber-daya sistem komputer
secara efisien, serta mampu berevolusi -- sistem operasi harus dibangun sehingga
memungkinkan dan memudahkan pengembangan, pengujian serta pengajuan sistemsistem
yang baru.
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5. 4 Sejarah Sistem Operasi
Menurut Tanenbaum, sistem operasi mengalami perkembangan yang sangat pesat,
yang dapat dibagi kedalam empat generasi:
• Generasi Pertama (1945-1955)
Generasi pertama merupakan awal perkembangan sistem komputasi elektronik
sebagai pengganti sistem komputasi mekanik, hal itu disebabkan kecepatan
manusia untuk menghitung terbatas dan manusia sangat mudah untuk membuat
kecerobohan, kekeliruan bahkan kesalahan. Pada generasi ini belum ada sistem
operasi, maka sistem komputer diberi instruksi yang harus dikerjakan secara
langsung.
• Generasi Kedua (1955-1965)
Generasi kedua memperkenalkan Batch Processing System, yaitu Job yang
dikerjakan dalam satu rangkaian, lalu dieksekusi secara berurutan.Pada generasi
ini sistem komputer belum dilengkapi sistem operasi, tetapi beberapa fungsi
sistem operasi telah ada, contohnya fungsi sistem operasi ialah FMS dan IBSYS.
• Generasi Ketiga (1965-1980)
Pada generasi ini perkembangan sistem operasi dikembangkan untuk melayani
banyak pemakai sekaligus, dimana para pemakai interaktif berkomunikasi lewat
terminal secara on-line ke komputer, maka sistem operasi menjadi multi-user (di
gunakan banyak pengguna sekali gus) dan multi-programming (melayani banyak
program sekali gus).
• Generasi Keempat (Pasca 1980an)
Dewasa ini, sistem operasi dipergunakan untuk jaringan komputer dimana
pemakai menyadari keberadaan komputer-komputer yang saling terhubung satu
sama lainnya. Pada masa ini para pengguna juga telah dinyamankan dengan
Graphical User Interface yaitu antar-muka komputer yang berbasis grafis yang
sangat nyaman, pada masa ini juga dimulai era komputasi tersebar dimana
komputasi-komputasi tidak lagi berpusat di satu titik, tetapi dipecah dibanyak
komputer sehingga tercapai kinerja yang lebih baik.
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5. 5 Perkembangan Perangkat Lunak Sistem Operasi
Paket operasi ataupun program yang dibuat dengan High Level Langguage,
seperti misalnya BASIC, FORTRAN, COBOL, dana Bahasa C dan lain sebagainya,
tidaka akan dapat dijalankan kalau tidak ada Operating System yang mendukungnya.
Sistem operasi ini akan mengatur semua proses dari sistem komputer.
1954. Sistem Operasi Yang Pertama Kali
Sistem operasi pertama kali dikembangkan pada sekitar tahun 1954 di General
Motor Research Laboratories untuk di gunakan pada komputer IBM 701. kemudian pada
tahun 1955, programmer di General Motor Research Laboratories bekerja sama dengan
North American Aviation menulis OS(operating System) untuk komputer IBM 704.
beberapa OS yang lainnya telah ditulis untuk komputer-komputer besar sejak dari tahun
1950 sampai dengan tahun 1960. OS tersebut terbatas pengguanaannya. Yaitu hanya
dapat digunakan untuk aplikasi pengolahan data secara sequential(urut) atau batch saja
dan biasanya dirancang untuk satu komputer saja.
1960. Sistem Operasi Untuk Komputer Mini Pertama Kali
OS untuk komputer mini pertama kali dikembangkan pada tahun 1960 bersamaan
dengan diproduksinya komputer-komputer mini. Sebelum tahun ini, OS hanya digunakan
untuk komputer-komputer besar (mainframe). Pada bulan April 1964, IBM
memperkenalkan OS yang disebut dengan OS/360 untuk dipergunakan pada semua seri
komputer 360.
1969. Unix
Pada tahun1969, Ken Thompson dari Bell Laboratories menulis suatu OS yang
disebut dengan UNIX. Yang diterapkan pada komputer PDP-. Pada tahun 1973, UNIX
dikembangkan dengan cara ditlis ulang dengan menggunakan bahasa C, sehingga
merupakan OS pertama yang ditulis dengan High Level Langguage. Sejak tahun tersebut,
banyak orang memperkirakan bahwa UNIX akan menjadi OS yang paling populer dan
akan banyak dipergunakan. UNIX merupakan OS untuk komputer 16-bit. UNIX pertama
kali diterapkan di mainframe computer dan mini computer.
1970. CP/M
Pada tahun 1970, komputer micro mulai dikembangkan dan bersamaan dengan
itu, perusahaan Digital Research mengembangkan OS yang diterapkan di komputer
mikro, yang disebut dengan CP/M. CP/M merupakan singkatan dari Control
Program/Microprocessor.
CP/M merupakan OS yang paling populer untuk komputer mikro 8-bit yang
mempergunakan microprocessor Zilog 80(Z80) atau microprocessor Intel 8080. CP/M
pada tahun 1976 diperbaiki dan lebih ditingkatkan dengan nama CP/M-80 dan karena
popularitasnya dan banyak di pergunakan, dianggap sebagai standar OS untuk komputer
8-bit. Penulis dari CP/M adalah Gary Kidall.
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1980. MS-DOS
Sebelum tahun 1980, OS yang paling banyak dipergunakan dan dianggap sebagai
standar dari OS adalah CP/M-80 buatan Digital Research. Tetapi sejak tahun 1980.
Microsoft Corporation di Bellevue, Washington yang dipakai oleh William Bill Gates.
Mengembangkan OS dengan nama MS-DOS (Microsoft-Disk Operating System) untuk
computer 16-bit. MS-DOS dipergunakan di komputer micro yang menggunakan
microprocessor Intel 8088 atau Intel 8086.
Merasa bahwa CP/M-80 yang dipergunakan di komputer 8-bit mulai banyak
ditinggalkan, Digital Research menegmbangkan OS yang baru dengan nama CP/M-86
untuk komputer 16-bit yang mempergunakan microprocessor Intel 8086 sebagai
penyaing MS-DOS.
OS lainnya yang dikembangkan oleh pabrik microsoft diantaranya adalah Xenix,
yang sebenarnya adalah Unix versi Microsoft untuk microprocessor Intel 8086, Zilog
8000 dan Motorola 68000. OS lainnya adalah:
- Oasis-16 dibuat oleh Phase One System.
- Pick OS dibuat oleh Pick System Inc.
- p-System dikembangkan pertama kali di university of california at san Diego pada
tahun 1974.
- TRS-DOS dibuat oleh Tandy Radio Shack.
1985. Microsoft Windows Yang Pertama
Perusahaan Microsoft memasarkan sistem operasi Windows versi yang pertama
pada tahun 1985. Windows sebagai sebuah sitem operasi sebenarnya belum bekerja
sepnuhnya sebagai platform, tetapi masih bekerja dibawah DOS. Ini berarti sebelum
Windows dioperasikan, sistem operasi DOS sudah harus digunakan terlebih dahulu yang
kemudian Windows dipanggil melalui DOS tersebut. Kelebihan Windows dari DOS
adalah kemudahannya untuk digunakan(user friendly) Karena menggunakan sistem GUI.
Multitasking( yaitu dapat mengerjakan program serentak dalam bentuk windows yang
dapat dipindah dari satu window ke window yang lain).
Walaupun demikian, windows versi 1.0 ini tidak populer dan kurang diminati
karena berbagai alasan, yang pertama adalah Windows 1.0 beroperasi dengan lambat
disebabkan pada waktu itu processor yang digunakan kurang mendukung. Yang kedua
adalah masih sedikitnya perangkat lunak yang ditulis untuk sistem operasi ini.
1987. IBM Operating System/2
IBM OS/2 dibuat oleh IBM untuk mengatasi kekurangan dari IBM PC-DOS atau
MS-DOS. Dengan microprocessor 80286 dan 80386. OS/2 dapat mengalamati memori
diatas batas 640 KB yang tidak dapat dilakukan oleh IBM PC-DOS. OS/2 mempunyai
beberapa kelebihan yaitu sebagai berikut:
- Dapat Mendukung beberapa aplikasi yang menggunakan memori sampai 16 MB
- Membuat manajemen basis data lebih mudah dengan menyediakan semua saranasarana
untuk membuat basis data.
- Dapat digunakan untuk network dengan dihubungkan pada beberapa host
Computer
- Dapat digunakan untuk multitasking, sehingga dari satu aplikasi ke aplikasi
lainnya.
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1988. Windows/386
Windows/386 dipekenalkan pada tahun 1988. Windows versi ini diharapkan dapat
membuat pengguna komputer berpindah dari DOS ke Windows, karena sudah didukung
oleh processor Intel 80386 yang sudah cukup cepat di komputer IBM PC/386.
1990. Windows 3.0
Mulai tahun 1990, popularitas Windows melalui Windows 3.0 meningkat dengan
cepat. Keberhasilan Windows 3.0 tidak terlepas dari dukungan processor Intel 80846
yang sudah cukup cepat di computer IBM PC/486. setahun kemudian pada tahun 1991,
Windows versi 3.1 diluncurkan untuk memperbaiki versi sebelumnya.
1993. Mosaic, Browser Internet Pertama Di Sistem Windows
Pada tahun 1990-an system Windows yang digunakan adalah versi 3.x. Windows
3.x ini tidak memiliki protocol, untuk hubunagn ke internet. Sehinnga di perlukan
perangkat lunak khusus untuk menjelajah ke internet. Salah satunya adalah yang disebut
dengan browser. Mosaic merupakan browser yang diperkenalkan pada tahun 1993.
mosaic merupakan browser internet yang pertama disistem Windows.
1995. Windows 95
Microsoft mengeluarkan Windows 95 yang mempunyai beberapa kelebihan dari
Windows versi 3.x. Windows 95 sudah tidak beroperasi dibawah platform DOS,sehingga
operasinya lebih cepat dibandingkan dengan Windows versi sebelumnya.
1998. Windows 98
Windows 98 merupakan perbaikan dari Windows 95. windows 98 diperkenalkan
pada bulan September 1997.
2000. Linux
Linux adalah sebuah sistem operasi yang sangat mirip dengan sistem-sistem
UNIX, karena memang tujuan utama rancangan dari proyek Linux adalah UNIX
compatible. Sejarah Linux dimulai pada tahun 1991, ketika mahasiswa Universitas
Helsinki, Finlandia bernama Linus Benedict Torvalds menulis Linux, sebuah kernel
untuk prosesor 80386, prosesor 32-bit pertama dalam kumpulan CPU intel yang cocok
untuk PC.
Pada awal perkembangannya, source code Linux disediakan secara bebas melalui
internet. Hasilnya, pengembangan Linux merupakan kolaborasi para pengguna dari
seluruh dunia, semuanya dilakukan secara eksklusif melalui internet. Bermula dari kernel
awal yang hanya mengimplementasikan subset kecil dari sistem UNIX, kini sistem Linux
telah tumbuh sehingga mampu memasukkan banyak fungsi UNIX.
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Kernel Linux terdistribusi di bawah Lisensi Publik Umum GNU (GPL), dimana
peraturannya disusun oleh Free Software Foundation. Linux bukanlah perangkat lunak
domain publik: Public Domain berarti bahwa pengarang telah memberikan copyright
terhadap perangkat lunak mereka, tetapi copyright terhadap kode Linux masih dipegang
oleh pengarang-pengarang kode tersebut. Linux adalah perangkat lunak bebas, namun:
bebas dalam arti bahwa siapa saja dapat mengkopi, modifikasi, memakainya dengan cara
apa pun, dan memberikan kopi mereka kepada siapa pun tanpa larangan atau halangan.
Implikasi utama peraturan lisensi Linux adalah bahwa siapa saja yang
menggunakan Linux, atau membuat modifikasi dari Linux, tidak boleh membuatnya
menjadi hak milik sendiri. Jika sebuah perangkat lunak dirilis berdasarkan lisensi GPL,
produk tersebut tidak boleh didistribusi hanya sebagai produk biner (binary-only).
Perangkat lunak yang dirilis atau akan dirilis tersebut harus disediakan sumber kodenya
bersamaan dengan distribusi binernya.
Gambar 11.Logo Linux
5. 6 Layanan Sistem Operasi
Sebuah sistem operasi yang baik menurut Tanenbaum harus memiliki layanan
sebagai berikut: pembuatan program, eksekusi program, pengaksesan I/O Device,
pengaksesan terkendali terhadap berkas pengaksesan sistem, deteksi dan pemberian
tanggapan pada kesalahan, serta akunting.
Pembuatan program yaitu sistem operasi menyediakan fasilitas dan layanan untuk
membantu para pemrogram untuk menulis program; Eksekusi Program yang berarti
Instruksi-instruksi dan data-data harus dimuat ke memori utama, perangkat-parangkat
masukan/ keluaran dan berkas harus di-inisialisasi, serta sumber-daya yang ada harus
disiapkan, semua itu harus di tangani oleh sistem operasi; Pengaksesan I/O Device,
artinya Sistem Operasi harus mengambil alih sejumlah instruksi yang rumit dan sinyal
kendali menjengkelkan agar pemrogram dapat berfikir sederhana dan perangkat pun
dapat beroperasi; Pengaksesan terkendali terhadap berkas yang artinya disediakannya
mekanisme proteksi terhadap berkas untuk mengendalikan pengaksesan terhadap berkas;
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Pengaksesan sistem artinya pada pengaksesan digunakan bersama (shared
system); Fungsi pengaksesan harus menyediakan proteksi terhadap sejumlah sumber-daya
dan data dari pemakai tak terdistorsi serta menyelesaikan konflik-konflik dalam
perebutan sumber-daya; Deteksi dan Pemberian tanggapan pada kesalahan, yaitu jika
muncul permasalahan muncul pada sistem komputer maka sistem operasi harus
memberikan tanggapan yang menjelaskan kesalahan yang terjadi serta dampaknya
terhadap aplikasi yang sedang berjalan; dan Akunting yang artinya Sistem Operasi yang
bagus mengumpulkan data statistik penggunaan beragam sumber-daya dan memonitor
parameter kinerja.
VI. APLIKASI
6. 1 Perkembangan Perangkat Lunak Paket Aplikasi
Sejak beredarnya computer personal,telah ribuan macam perangkat lunak untuk
bermacam-macam keperluan aplikasi tersedia di pasaran guna memenuhi kebutuhan para
pemakai computer.
1976. Electric Pencil.
Pada tahun ini, Michael Shrayer memperkenalkan suatu program pengolah kata
(word processor) yang diberi nama Electric pencil. Electric pencil pada mulanya hanya
untuk computer mikro altair saja, tetapi kemudian dikembangkan untuk computerkomputer
mikro yang lainnya dan sejumlah alat cetak (printer), semuanya sampai dengan
78 versi. Electric pencil tidak dapat menembus pasaran karena kurang popular. Electric
pencil merupakan paket pengolah kata yang pertama dan sampai 2 tahun kemuduan
merupkan paket pengolah kata satu-satunya yang beredar dipasaran.
1979. Word Star
John Barnaby menulis program pengolah kata atas permintaan Seymour
Rubinstein. Sebelum menulis program, Seymour Rubinstein telah mengunjungi beberapa
penjual perangkat lunak untuk menegtahui keinginan masyarakat tentang software
pengolah kata. Program paket tersebut kemudian disebut Word Star dan sukses
menembus pasaran dengan perusahaannya yang bernama micropo. Beberapa versi Word
Star telah beredar dipasaran, diantaranya Word Star release 3.4, Word Star profesional
release 4.0 dan lain sebagainya.
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1979. Apple Writer
Apple Writer juga merupkan program paket pengolah kata yang habis terjual.
Apple Writer ditulis oleh Paul Lutus yang nyentrik. Paul Lutus merupkan programmer
yang independen.
1979. VisiCalc
Pada tanggal 11 mei 1979 pada west coast computer fair, paket program
spreadsheet pertama yang dirancang untuk pemakai komputer personal telah
diperkenalkan dengan nama VisiCalc(Visible calculator atau visual calculator). VisiCalc
merupakan ide dari Daniel Bricklin dan dibuat oleh Robert Frankston. Daniel Bricklin
adalah seseorang lulusan dari MIT yang sudah bekerja sebagai software engineer di
peruasahaan komputer Digital Equipment Corporation (DEC) yang kemudian mengikuti
kuliah kembali di Harvard Businees School.
1981. dBASE-II
Wayne Ratliff, ahli tehnik NASA menulis suatu program untuk aplikasi bisnis
pada waktu-waktu senggangnya dan memasarkannya dengan nama vulcan,tetapi tidak
sukses di pasaran.
Sementara George Tate, ahli didalam mereparasi komputer yang kemudian
menjadi ahli pemasaran software bersama-sama dengan Hal Lachlee mengadakan
kontrak dengan Wayne Ratliff untuk memasarkan Vulcan. Nama Vulcan kemudian
dirubah menjadi dBASE-II. Supaya seakan-akan merupakan software yang terbaru,dari
peningkatan dBASE sebelumnya, padahal dBASE-I tidak pernah ada. dBASE-II
dipasarkan pada tahun 1981 dengan nama perusahaannya Ashton-Tate yang sebenarnya
merupakan paket DBMS(Database Management Systems) yang mempunyai bahasa
tingkat tinggi.
1982. LOTUS 1-2-3
Lotus 1-2-3 merupakan suatu program paket yang berisi gabungan programprogram
spreadsheet. Grafik dan kemampuan untuk mendapatkan informasi, yaitu tiga
bentuk program dalam satu program. Lotus 1-2-3 ditulis oleh mitchell kapor, lulusan dari
yale University tahun 1971 lotus 1-2-3 khusus ditulis untuk komputer mikro 16 bit IBM
PC..
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Berikut ini adalah beberapa macam paket software untuk komputer IBM PC atau yang
kompatibel dengan IBM PC.
1. Aplikasi Untuk Pengolah Kata:
Microsof Word, Final Word,Easy writer II,NBI word processing,Word
Vision,Word Star, Textplus, dan lain-lain.
Gambar 12. Microsof Word
2. Aplikasi Untuk Database Dan File Management:
Advanced Db master,Advanced System PAC,Aladin,Data Ace,dBASE-III,Easy
Filler,Visifile,dan lain-lain.
Gambar 13. dBASE-III
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3. Aplikasi Untuk Permodelan:
Calc-86,Construction Models, Microsoft Window, Symphony,Vizualize, VIZA-
CON, The Thinker, dan lain-lain.
4. Aplikasi Untuk Investasi Manajemen:
Finacial Fastrax, Financial Software series,Market Maverick,
Optioncalc,stockcal, dan lain-lain.
5. Aplikasi Untuk Akuntansi:
Account payable,Colorbiz Inventory,Gneral Ledger System,Inventory control,
Versainventory, dan lain-lain.
6. Aplikasi Penjadwalan Proyek:
Microgantt,Shoebox,Time Scheduler, Visischedule, dan lain-lain.
7. Aplikasi Untuk Komunikasi Dan Telekomunikasi:
Ascom, Ethernet,The Micro Link II, Microterm,Move-it, dan lain-lain.
8. Aplikasi Untuk Garfik:
Auto Cad, Business Graphics, Corel Draw, Pc-Draw,Graph Magic, Pyxel
Visual, Adobe Photoshop, Fast Graph, dan lain-lain.
9. Aplikasi Untuk Manipulasi Printer:
Letrrix, Fancy Font, Nice Print, Select A Font, Printer Boss,Side Ways, dan
lain-lain.
10. Aplikasi Untuk Manfaat :
Autodex, Sevenware, Side Kick, The Spooler, Super key,System Backup, UT-
86,The Norton Utilities, dan lain-lain.
11. Aplikasi Untuk Sorting:
Autosort, fatsort,HBsort, the Sort, The Sorter, dan lain-lain.
12. Aplikasi Untuk Pendidikan:
FaceMaker, Math Drills,Pc Pal, Pc pilot,Video Etch,Word Whiz, dan lain-lain.
13. Aplikasi Untuk Permainan:
Apple Panic, jumpman,Miliionaire,space minner,zork, flight simulator,train
simulator, dan lain-lain.
14. Aplikasi Untuk Statistic:
BMD,Microstat,SPSS, Statpro, TSP, SAS, dan lain-lain.
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Daftar Pustaka
Sutanta,Edhy,2005, Pengantar Teknologi Informasi, Graha Ilmu,Yogyakarta
E.S Margianti, D. Suryadi H.S, 1994, Sistem Informasi Manajemen, Gunadarma, Jakarta
Hartono,Jogiyanto, 1999, Pengenalan Komputer, Andi Jogyakarta, Yogyakarta
1. Dibawah ini yang termasuk alat input, kecuali…
a. Mouse b. Keyboard
c. Printer * d. Scanner
2. Bagian dari system computer yang berfungsi untuk mencatat hasil pengolahan data
adalah…
a. Unit Input b. Unit Output *
c. CPU d. Secondary Storage
3. Alat apakah yang digunakan untuk mengatasi masalah kapasitas floppy disk...
a. Zip Drive * b. CD-Room
c. Hard Disk d. DVD
4. Disebut Apakah alat yang digunakan untuk mencetak tulisan dan image pada media
kertas atau film…
a. Soft copy device b. Hard copy device *
c. printer d. Plotter
5. Soft copy device adalah alat untuk…
a. Mencetak pada kertas b. Mencetak pada media lunak *
c. Mencetak pada film d. Mencetak pada media keras
6. Diantara type printer dibawah ini yang termasuk printer berkecepatan tinggi adalah...
a. Line printer * b. Dot matrix printer
c. Inkjet Printer d. Daisy wheel printer
7. Pada tahun berapakah system operasi pertama kali di kembangkan...
a. 1945 b. 1960
c. 1965 d. 1954 *
8. Sistem operasi apakah yang pertama kali menggunakan high level langguage...
a. Windows b. Linux
c. Unix * d. MS-Dos
9. Dibawah ini mana yang bukan termasuk paket pengolah kata (word processor)…
30
a. VisiCalc * b. Electric Pencil
c. Word Star d. Microsoft Word
10. Dibawah ini manakah yang merupakan paket aplikasi untuk pendidikan…
a. Fancy font b. Math Drils *
c. SAS d. MicroTerm

II.SISTEM KOMPUTER
A.KOMPONEN SISTEM KOMPUTER
 Perangkat Keras
 Piranti Lunak
 Data dan Informasi
 Prosedur
 Manusia

B.PERANGKAT KERAS (HARDWARE)
Adalah peralatan fisik yang membentuk suatu sistem komputer.
Komponen-komponennya :
 Input Devices (Peralatan Input)
 Memory (Memori)
 Processors (Prosesor)
 Output Devices (Peralatan Output)
 Storage Devices (Peralatan Penyimpanan)
 Communication Devices (Peralatan Komunikasi)
 Diagram hubungan antar komponen Perangkat Keras











III.PERBEDAAN ARSITEKTUR DAN ORGANISASI KOMPUTER
1. Arsitektur Komputer berkaitan erat dengan atribut-atribut sebuah sistem yang tampak (Visible) bagi seorang program.
Contoh Atribut Arsitektural Adalah :set instruksi, jumlah bit utk representasi bermacam jenis data, mekanisme I/O, dan teknik-teknik pengalamatan memory.
2. Organisasi Komputer berkaitan erat dengan unit-unit operasional dan interkoneksinya yang merealisasikan spesifikasi arsitektural.
Contoh Atribut Organisasional Adalah :rincian hardware yang dapat diketahui oleh pemrogram, seperti sinyal kontrol, interface komputer, dan teknologi memori yang digunakan.

IV.STRUKTUR DAN FUNGSI KOMPUTER
Fungsi  Operasi masing-masing komponen sebagai bagian dari struktur.
Empat (4) fungsi dasar pada sebuah komputer
a. Olah Data
b. Simpan Data
c. Pindah Data
d. Kontrol
Struktur  Cara komponen-komponen saling terkait.
Empat (4) Komponen Utama
1. Central Processing Unit
Komponen Utama Dari CPU  Control Unit, ALU, Register, CPU Interconnection
2. Main Memory
Komponen Utama Dari Memory  Internal Memory, dan External Memory
3. Input Output
Komponen Utama Dari I/O 
4. System Interconnection
Komponen Utama Dari I/O

V. MESIN VON NEUMANN
Memiliki ciri-ciri sebagai berikut :
1. Menggunakan Stored Program Concept
2. Mengacu pada IAS Computer (Gambar struktur komputer IAS)
3. Struktur IAS Computer terdiri dari :
a. Main Memory (RAM)  tempat menampung data dan instruksi untuk pemrosesan lebih lanjut.

JENIS-JENISNYA 
 RAM (Random Access Memory), DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), EDO RAM (Extended Data Out RAM).
 ROM (Read Only Memory), ROM Programmable Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory)
 Circuit Board: SIMM, DIMM
 Cache Memory (Flash RAM)
 Video Memory (VRAM)
 Flash Memory

REPRESENTASI DATA DI DALAM MEMORI.
 Pengertian binary digits.
 Sistem bilangan biner.
 Sistem pengkodean bilangan/ characters: EBCDIC, ASCII (8 bits), Unicode (16 bits).
 Ukuran memori  Bit, Byte, Kilobyte (KB), Megabyte (MB), Gigabyte (GB), Terabyte (TB)
b. ALU
c. Control Unit yang menginterpretasikan instruksi2 menyebabkan instruksi tsb dieksekusi.
d. I/O Device yang dioperasikan oleh control unit

VI. KONSEP HARDWARE
1. SISD  single instruction stream & single data stream – semua unit processor tradisional – PC & mainframe.
2. SIMD  mengacu pada array processor dengan unit instruksi tunggal yang mengambil instruksi dan kemudian memerintahkan beberapa unit data  untuk secara paralel menangani datanya masing-masing.
Kegunaan  komputasi yang mengulang dan kalkulasi yang sama pada banyak set data.
Contohnya  menambahkan semua elemen dari 64 vektor yang independen.
Beberapa superkomputer merupakan SIMD.
3. MISD  tidak satupun komputer sekarang ini yang sesuai dengan model ini.
4. MIMD  sekelompok komputer yang independen dengan masing-masing program counter, program dan data. Semua sistem terdistribusi adalah MIMD.
MIMD dibagi menjadi 2 grup:
a. Multiprocessor yang menggunakan memory bersama.
b. Multicomputer.

PERTEMUAN 2

September 1990 Order Number: 231455-005
8086
16-BIT HMOS MICROPROCESSOR
8086/8086-2/8086-1
Y Direct Addressing Capability 1 MByte
of Memory
Y Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y 14 Word, by 16-Bit Register Set with
Symmetrical Operations
Y 24 Operand Addressing Modes
Y Bit, Byte, Word, and Block Operations
Y 8 and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Y Range of Clock Rates:
5 MHz for 8086,
8 MHz for 8086-2,
10 MHz for 8086-1
Y MULTIBUS System Compatible
Interface
Y Available in EXPRESS
ÐStandard Temperature Range
ÐExtended Temperature Range
Y Available in 40-Lead Cerdip and Plastic
Package
(See Packaging Spec. Order Ý231369)
The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin
CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations
to achieve high performance levels.
231455±1 Figure 1. 8086 CPU Block Diagram
231455±2
40 Lead
Figure 2. 8086 Pin
Configuration
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8086
Table 1. Pin Description
The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ``Local
Bus'' in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to
additional bus buffers).
Symbol Pin No. Type Name and Function
AD15±AD0 2±16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address (T1), and data (T2, T3, TW, T4) bus. A0 is
analogous to BHE for the lower byte of the data bus, pins D7±D0. It is
LOW during T1 when a byte is to be transferred on the lower portion
of the bus in memory or I/O operations. Eight-bit oriented devices tied
to the lower half would normally use A0 to condition chip select
functions. (See BHE.) These lines are active HIGH and float to 3-state
OFF during interrupt acknowledge and local bus ``hold acknowledge''.
A19/S6, 35±38 O ADDRESS/STATUS: During T1 these are the four most significant
A18/S5, address lines for memory operations. During I/O operations these
A17/S4, lines are LOW. During memory and I/O operations, status information
A16/S3 is available on these lines during T2, T3, TW, T4. The status of the
interrupt enable FLAG bit (S5) is updated at the beginning of each
CLK cycle. A17/S4 and A16/S3 are encoded as shown.
This information indicates which relocation register is presently being
used for data accessing.
These lines float to 3-state OFF during local bus ``hold acknowledge.''
A17/S4 A16/S3 Characteristics
0 (LOW) 0 Alternate Data
0 1 Stack
1 (HIGH) 0 Code or None
1 1 Data
S6 is 0
(LOW)
BHE/S7 34 O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal
(BHE) should be used to enable data onto the most significant half of
the data bus, pins D15±D8. Eight-bit oriented devices tied to the upper
half of the bus would normally use BHE to condition chip select
functions. BHE is LOW during T1 for read, write, and interrupt
acknowledge cycles when a byte is to be transferred on the high
portion of the bus. The S7 status information is available during T2,
T3, and T4. The signal is active LOW, and floats to 3-state OFF in
``hold''. It is LOW during T1 for the first interrupt acknowledge cycle.
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None
RD 32 O READ: Read strobe indicates that the processor is performing a
memory or I/O read cycle, depending on the state of the S2 pin. This
signal is used to read devices which reside on the 8086 local bus. RD
is active LOW during T2, T3 and TW of any read cycle, and is
guaranteed to remain HIGH in T2 until the 8086 local bus has floated.
This signal floats to 3-state OFF in ``hold acknowledge''.
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8086
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
READY 22 I READY: is the acknowledgement from the addressed memory or I/O
device that it will complete the data transfer. The READY signal from
memory/IO is synchronized by the 8284A Clock Generator to form
READY. This signal is active HIGH. The 8086 READY input is not
synchronized. Correct operation is not guaranteed if the setup and hold
times are not met.
INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table located in
system memory. It can be internally masked by software resetting the
interrupt enable bit. INTR is internally synchronized. This signal is
active HIGH.
TEST 23 I TEST: input is examined by the ``Wait'' instruction. If the TEST input is
LOW execution continues, otherwise the processor waits in an ``Idle''
state. This input is synchronized internally during each clock cycle on
the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which causes
a type 2 interrupt. A subroutine is vectored to via an interrupt vector
lookup table located in system memory. NMI is not maskable internally
by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.
RESET 21 I RESET: causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock cycles. It
restarts execution, as described in the Instruction Set description, when
RESET returns LOW. RESET is internally synchronized.
CLK 19 I CLOCK: provides the basic timing for the processor and bus controller.
It is asymmetric with a 33% duty cycle to provide optimized internal
timing.
VCC 40 VCC: a5V power supply pin.
GND 1, 20 GROUND
MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to
operate in. The two modes are discussed in the following sections.
The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MX eVSS).
Only the pin functions which are unique to maximum mode are described; all other pin functions are as
described above.
S2, S1, S0 26±28 O STATUS: active during T4, T1, and T2 and is returned to the passive state
(1, 1, 1) during T3 or during TW when READY is HIGH. This status is used
by the 8288 Bus Controller to generate all memory and I/O access control
signals. Any change by S2, S1, or S0 during T4 is used to indicate the
beginning of a bus cycle, and the return to the passive state in T3 or TW is
used to indicate the end of a bus cycle.
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8086
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
S2, S1, S0 26±28 O These signals float to 3-state OFF in ``hold acknowledge''. These status
(Continued) lines are encoded as shown.
S2 S1 S0 Characteristics
0 (LOW) 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 (HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
RQ/GT0, 30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force
RQ/GT1 the processor to release the local bus at the end of the processor's
current bus cycle. Each pin is bidirectional with RQ/GT0 having higher
priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and
may be left unconnected. The request/grant sequence is as follows
(see Page 2-24):
1. A pulse of 1 CLK wide from another local bus master indicates a local
bus request (``hold'') to the 8086 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086 to
the requesting master (pulse 2), indicates that the 8086 has allowed the
local bus to float and that it will enter the ``hold acknowledge'' state at
the next CLK. The CPU's bus interface unit is disconnected logically
from the local bus during ``hold acknowledge''.
3. A pulse 1 CLK wide from the requesting master indicates to the 8086
(pulse 3) that the ``hold'' request is about to end and that the 8086 can
reclaim the local bus at the next CLK.
Each master-master exchange of the local bus is a sequence of 3
pulses. There must be one dead CLK cycle after each bus exchange.
Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it
will release the local bus during T4 of the cycle when all the following
conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge
sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events
will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW. The LOCK signal
is activated by the ``LOCK'' prefix instruction and remains active until the
completion of the next instruction. This signal is active LOW, and floats
to 3-state OFF in ``hold acknowledge''.
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8086
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
QS1, QS0 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after
which the queue operation is performed.
QS1 and QS0 provide status to allow external tracking of the internal
8086 instruction queue.
QS1 QS0 Characteristics
0 (LOW) 0 No Operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent Byte from Queue
The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX eVCC). Only the pin
functions which are unique to minimum mode are described; all other pin functions are as described above.
M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to
distinguish a memory access from an I/O access. M/IO becomes valid in
the T4 preceding a bus cycle and remains valid until the final T4 of the cycle
(M e HIGH, IO e LOW). M/IO floats to 3-state OFF in local bus ``hold
acknowledge''.
WR 29 O WRITE: indicates that the processor is performing a write memory or write
I/O cycle, depending on the state of the M/IO signal. WR is active for T2, T3
and TW of any write cycle. It is active LOW, and floats to 3-state OFF in
local bus ``hold acknowledge''.
INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active
LOW during T2, T3 and TW of each interrupt acknowledge cycle.
ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch the
address into the 8282/8283 address latch. It is a HIGH pulse active during
T1 of any bus cycle. Note that ALE is never floated.
DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that desires to
use an 8286/8287 data bus transceiver. It is used to control the direction of
data flow through the transceiver. Logically DT/R is equivalent to S1 in the
maximum mode, and its timing is the same as for M/IO. (T e HIGH, R e
LOW.) This signal floats to 3-state OFF in local bus ``hold acknowledge''.
DEN 26 O DATA ENABLE: provided as an output enable for the 8286/8287 in a
minimum system which uses the transceiver. DEN is active LOW during
each memory and I/O access and for INTA cycles. For a read or INTA cycle
it is active from the middle of T2 until the middle of T4, while for a write cycle
it is active from the beginning of T2 until the middle of T4. DEN floats to 3-
state OFF in local bus ``hold acknowledge''.
HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus ``hold.'' To be
HLDA acknowledged, HOLD must be active HIGH. The processor receiving the
``hold'' request will issue HLDA (HIGH) as an acknowledgement in the
middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines. After HOLD is
detected as being LOW, the processor will LOWer the HLDA, and when the
processor needs to run another cycle, it will again drive the local bus and
control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up
resistors.
The same rules as for RQ/GT apply regarding when the local bus will be
released.
HOLD is not an asynchronous input. External synchronization should be
provided if the system cannot otherwise guarantee the setup time.
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8086
FUNCTIONAL DESCRIPTION
General Operation
The internal functions of the 8086 processor are
partitioned logically into two processing units. The
first is the Bus Interface Unit (BIU) and the second is
the Execution Unit (EU) as shown in the block diagram
of Figure 1.
These units can interact directly but for the most
part perform as separate asynchronous operational
processors. The bus interface unit provides the functions
related to instruction fetching and queuing, operand
fetch and store, and address relocation. This
unit also provides the basic bus control. The overlap
of instruction pre-fetching provided by this unit
serves to increase processor performance through
improved bus bandwidth utilization. Up to 6 bytes of
the instruction stream can be queued while waiting
for decoding and execution.
The instruction stream queuing mechanism allows
the BIU to keep the memory utilized very efficiently.
Whenever there is space for at least 2 bytes in the
queue, the BIU will attempt a word fetch memory
cycle. This greatly reduces ``dead time'' on the
memory bus. The queue acts as a First-In-First-Out
(FIFO) buffer, from which the EU extracts instruction
bytes as required. If the queue is empty (following a
branch instruction, for example), the first byte into
the queue immediately becomes available to the EU.
The execution unit receives pre-fetched instructions
from the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are
passed through the BIU for processing by the EU,
which passes results to the BIU for storage. See the
Instruction Set description for further register set
and architectural descriptions.
MEMORY ORGANIZATION
The processor provides a 20-bit address to memory
which locates the byte being referenced. The memory
is organized as a linear array of up to 1 million
bytes, addressed as 00000(H) to FFFFF(H). The
memory is logically divided into code, data, extra
data, and stack segments of up to 64K bytes each,
with each segment falling on 16-byte boundaries.
(See Figure 3a.)
All memory references are made relative to base addresses
contained in high speed segment registers.
The segment types were chosen based on the addressing
needs of programs. The segment register
to be selected is automatically chosen according to
the rules of the following table. All information in one
segment type share the same logical attributes (e.g.
code or data). By structuring memory into relocatable
areas of similar characteristics and by automatically
selecting segment registers, programs are
shorter, faster, and more structured.
Word (16-bit) operands can be located on even or
odd address boundaries and are thus not constrained
to even boundaries as is the case in many
16-bit computers. For address and data operands,
the least significant byte of the word is stored in the
lower valued address location and the most significant
byte in the next higher address location. The
BIU automatically performs the proper number of
memory accesses, one if the word operand is on an
even byte boundary and two if it is on an odd byte
boundary. Except for the performance penalty, this
double access is transparent to the software. This
performance penalty does not occur for instruction
fetches, only word operands.
Physically, the memory is organized as a high bank
(D15±D8) and a low bank (D7±D0) of 512K 8-bit
bytes addressed in parallel by the processor's address
lines A19±A1. Byte data with even addresses
is transferred on the D7±D0 bus lines while odd addressed
byte data (A0 HIGH) is transferred on the
D15±D8 bus lines. The processor provides two enable
signals, BHE and A0, to selectively allow reading
from or writing into either an odd byte location,
even byte location, or both. The instruction stream is
fetched from memory as words and is addressed
internally by the processor to the byte level as necessary.
Memory Segment Register Segment
Reference Need Used Selection Rule
Instructions CODE (CS) Automatic with all instruction prefetch.
Stack STACK (SS) All stack pushes and pops. Memory references relative to BP
base register except data references.
Local Data DATA (DS) Data references when: relative to stack, destination of string
operation, or explicitly overridden.
External (Global) Data EXTRA (ES) Destination of string operations: explicitly selected using a
segment override.
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8086
231455±3
Figure 3a. Memory Organization
In referencing word data the BIU requires one or two
memory cycles depending on whether or not the
starting byte of the word is on an even or odd address,
respectively. Consequently, in referencing
word operands performance can be optimized by locating
data on even address boundaries. This is an
especially useful technique for using the stack, since
odd address references to the stack may adversely
affect the context switching time for interrupt processing
or task multiplexing.
231455±4
Figure 3b. Reserved Memory Locations
Certain locations in memory are reserved for specific
CPU operations (see Figure 3b). Locations from
address FFFF0H through FFFFFH are reserved for
operations including a jump to the initial program
loading routine. Following RESET, the CPU will always
begin execution at location FFFF0H where the
jump must be. Locations 00000H through 003FFH
are reserved for interrupt operations. Each of the
256 possible interrupt types has its service routine
pointed to by a 4-byte pointer element consisting of
a 16-bit segment address and a 16-bit offset address.
The pointer elements are assumed to have
been stored at the respective places in reserved
memory prior to occurrence of interrupts.
MINIMUM AND MAXIMUM MODES
The requirements for supporting minimum and maximum
8086 systems are sufficiently different that
they cannot be done efficiently with 40 uniquely defined
pins. Consequently, the 8086 is equipped with
a strap pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the
pins changes dependent on the condition of the
strap pin. When MN/MX pin is strapped to GND, the
8086 treats pins 24 through 31 in maximum mode.
An 8288 bus controller interprets status information
coded into S0, S2, S2 to generate bus timing and
control signals compatible with the MULTIBUS architecture.
When the MN/MX pin is strapped to VCC,
the 8086 generates bus control signals itself on pins
24 through 31, as shown in parentheses in Figure 2.
Examples of minimum mode and maximum mode
systems are shown in Figure 4.
BUS OPERATION
The 8086 has a combined address and data bus
commonly referred to as a time multiplexed bus.
This technique provides the most efficient use of
pins on the processor while permitting the use of a
standard 40-lead package. This ``local bus'' can be
buffered directly and used throughout the system
with address latching provided on memory and I/O
modules. In addition, the bus can also be demultiplexed
at the processor with a single set of address
latches if a standard non-multiplexed bus is desired
for the system.
Each processor bus cycle consists of at least four
CLK cycles. These are referred to as T1, T2, T3 and
T4 (see Figure 5). The address is emitted from the
processor during T1 and data transfer occurs on the
bus during T3 and T4. T2 is used primarily for changing
the direction of the bus during read operations. In
the event that a ``NOT READY'' indication is given
by the addressed device, ``Wait'' states (TW) are inserted
between T3 and T4. Each inserted ``Wait''
state is of the same duration as a CLK cycle. Periods
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8086
231455±5
Figure 4a. Minimum Mode 8086 Typical Configuration
231455±6
Figure 4b. Maximum Mode 8086 Typical Configuration
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8086
can occur between 8086 bus cycles. These are referred
to as ``Idle'' states (Ti) or inactive CLK cycles.
The processor uses these cycles for internal housekeeping.
During T1 of any bus cycle the ALE (Address Latch
Enable) signal is emitted (by either the processor or
the 8288 bus controller, depending on the MN/MX
strap). At the trailing edge of this pulse, a valid address
and certain status information for the cycle
may be latched.
Status bits S0, S1 , and S2 are used, in maximum
mode, by the bus controller to identify the type of
bus transaction according to the following table:
S2 S1 S0 Characteristics
0 (LOW) 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 (HIGH) 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)
231455±8
Figure 5. Basic System Timing
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8086
Status bits S3 through S7 are multiplexed with highorder
address bits and the BHE signal, and are
therefore valid during T2 through T4. S3 and S4 indicate
which segment register (see Instruction Set description)
was used for this bus cycle in forming the
address, according to the following table:
S4 S3 Characteristics
0 (LOW) 0 Alternate Data (extra segment)
0 1 Stack
1 (HIGH) 0 Code or None
1 1 Data
S5 is a reflection of the PSW interrupt enable bit.
S6 e 0 and S7 is a spare status bit.
I/O ADDRESSING
In the 8086, I/O operations can address up to a
maximum of 64K I/O byte registers or 32K I/O word
registers. The I/O address appears in the same format
as the memory address on bus lines A15±A0.
The address lines A19±A16 are zero in I/O operations.
The variable I/O instructions which use register
DX as a pointer have full address capability while
the direct I/O instructions directly address one or
two of the 256 I/O byte locations in page 0 of the
I/O address space.
I/O ports are addressed in the same manner as
memory locations. Even addressed bytes are transferred
on the D7±D0 bus lines and odd addressed
bytes on D15±D8. Care must be taken to assure that
each register within an 8-bit peripheral located on
the lower portion of the bus be addressed as even.
External Interface
PROCESSOR RESET AND INITIALIZATION
Processor initialization or start up is accomplished
with activation (HIGH) of the RESET pin. The 8086
RESET is required to be HIGH for greater than 4
CLK cycles. The 8086 will terminate operations on
the high-going edge of RESET and will remain dormant
as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence
for approximately 10 CLK cycles. After this
interval the 8086 operates normally beginning with
the instruction in absolute location FFFF0H (see Figure
3b). The details of this operation are specified in
the Instruction Set description of the MCS-86 Family
User's Manual. The RESET input is internally synchronized
to the processor clock. At initialization the
HIGH-to-LOW transition of RESET must occur no
sooner than 50 ms after power-up, to allow complete
initialization of the 8086.
NMI asserted prior to the 2nd clock after the end of
RESET will not be honored. If NMI is asserted after
that point and during the internal reset sequence,
the processor may execute one instruction before
responding to the interrupt. A hold request active
immediately after RESET will be honored before the
first instruction fetch.
All 3-state outputs float to 3-state OFF during
RESET. Status is active in the idle state for the first
clock after RESET becomes active and then floats
to 3-state OFF. ALE and HLDA are driven low.
INTERRUPT OPERATIONS
Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts
and software aspects of hardware interrupts are
specified in the Instruction Set description. Hardware
interrupts can be classified as non-maskable or
maskable.
Interrupts result in a transfer of control to a new program
location. A 256-element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH
(see Figure 3b), which are reserved for this purpose.
Each element in the table is 4 bytes in size and
corresponds to an interrupt ``type''. An interrupting
device supplies an 8-bit type number, during the interrupt
acknowledge sequence, which is used to
``vector'' through the appropriate element to the new
interrupt service program location.
NON-MASKABLE INTERRUPT (NMI)
The processor provides a single non-maskable interrupt
pin (NMI) which has higher priority than the
maskable interrupt request pin (INTR). A typical use
would be to activate a power failure routine. The
NMI is edge-triggered on a LOW-to-HIGH transition.
The activation of this pin causes a type 2 interrupt.
(See Instruction Set description.)
NMI is required to have a duration in the HIGH state
of greater than two CLK cycles, but is not required to
be synchronized to the clock. Any high-going transition
of NMI is latched on-chip and will be serviced
at the end of the current instruction or between
whole moves of a block-type instruction. Worst case
response to NMI would be for multiply, divide, and
variable shift instructions. There is no specification
on the occurrence of the low-going edge; it may occur
before, during, or after the servicing of NMI. Another
high-going edge triggers another response if it
occurs after the start of the NMI procedure. The signal
must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
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8086
MASKABLE INTERRUPT (INTR)
The 8086 provides a single interrupt request input
(INTR) which can be masked internally by software
with the resetting of the interrupt enable FLAG
status bit. The interrupt request signal is level triggered.
It is internally synchronized during each clock
cycle on the high-going edge of CLK. To be responded
to, INTR must be present (HIGH) during
the clock period preceding the end of the current
instruction or the end of a whole move for a blocktype
instruction. During the interrupt response sequence
further interrupts are disabled. The enable
bit is reset as part of the response to any interrupt
(INTR, NMI, software interrupt or single-step), although
the FLAGS register which is automatically
pushed onto the stack reflects the state of the processor
prior to the interrupt. Until the old FLAGS register
is restored the enable bit will be zero unless
specifically set by an instruction.
During the response sequence (Figure 6) the processor
executes two successive (back-to-back) interrupt
acknowledge cycles. The 8086 emits the LOCK
signal from T2 of the first bus cycle until T2 of the
second. A local bus ``hold'' request will not be honored
until the end of the second bus cycle. In the
second bus cycle a byte is fetched from the external
interrupt system (e.g., 8259A PIC) which identifies
the source (type) of the interrupt. This byte is multiplied
by four and used as a pointer into the interrupt
vector lookup table. An INTR signal left HIGH will be
continually responded to within the limitations of the
enable bit and sample period. The INTERRUPT RETURN
instruction includes a FLAGS pop which returns
the status of the original interrupt enable bit
when it restores the FLAGS.
HALT
When a software ``HALT'' instruction is executed the
processor indicates that it is entering the ``HALT''
state in one of two ways depending upon which
mode is strapped. In minimum mode, the processor
issues one ALE with no qualifying bus control signals.
In maximum mode, the processor issues appropriate
HALT status on S2, S1 , and S0; and the
8288 bus controller issues one ALE. The 8086 will
not leave the ``HALT'' state when a local bus ``hold''
is entered while in ``HALT''. In this case, the processor
reissues the HALT indicator. An interrupt request
or RESET will force the 8086 out of the ``HALT''
state.
READ/MODIFY/WRITE (SEMAPHORE)
OPERATIONS VIA LOCK
The LOCK status information is provided by the
processor when directly consecutive bus cycles are
required during the execution of an instruction.
This provides the processor with the capability
of performing read/modify/write operations on
memory (via the Exchange Register With Memory
instruction, for example) without the possibility of another
system bus master receiving intervening memory
cycles. This is useful in multi-processor system
configurations to accomplish ``test and set lock'' operations.
The LOCK signal is activated (forced LOW)
in the clock cycle following the one in which the software
``LOCK'' prefix instruction is decoded by the
EU. It is deactivated at the end of the last bus cycle
of the instruction following the ``LOCK'' prefix instruction.
While LOCK is active a request on a RQ/
GT pin will be recorded and then honored at the end
of the LOCK.
231455±9
Figure 6. Interrupt Acknowledge Sequence
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8086
EXTERNAL SYNCHRONIZATION VIA TEST
As an alternative to the interrupts and general I/O
capabilities, the 8086 provides a single softwaretestable
input known as the TEST signal. At any time
the program may execute a WAIT instruction. If at
that time the TEST signal is inactive (HIGH), program
execution becomes suspended while the processor
waits for TEST to become active. It must
remain active for at least 5 CLK cycles. The WAIT
instruction is re-executed repeatedly until that time.
This activity does not consume bus cycles. The
processor remains in an idle state while waiting. All
8086 drivers go to 3-state OFF if bus ``Hold'' is entered.
If interrupts are enabled, they may occur while
the processor is waiting. When this occurs the processor
fetches the WAIT instruction one extra time,
processes the interrupt, and then re-fetches and reexecutes
the WAIT instruction upon returning from
the interrupt.
Basic System Timing
Typical system configurations for the processor operating
in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to VCC and
the processor emits bus control signals in a manner
similar to the 8085. In maximum mode, the MN/MX
pin is strapped to VSS and the processor emits coded
status information which the 8288 bus controller
uses to generate MULTIBUS compatible bus control
signals. Figure 5 illustrates the signal timing relationships.
231455±10
Figure 7. 8086 Register Model
SYSTEM TIMINGÐMINIMUM SYSTEM
The read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal. The trailing (lowgoing)
edge of this signal is used to latch the address
information, which is valid on the local bus at
this time, into the address latch. The BHE and A0
signals address the low, high, or both bytes. From T1
to T4 the M/IO signal indicates a memory or I/O
operation. At T2 the address is removed from the
local bus and the bus goes to a high impedance
state. The read control signal is also asserted at T2.
The read (RD) signal causes the addressed device
to enable its data bus drivers to the local bus. Some
time later valid data will be available on the bus and
the addressed device will drive the READY line
HIGH. When the processor returns the read signal to
a HIGH level, the addressed device will again 3-
state its bus drivers. If a transceiver is required to
buffer the 8086 local bus, signals DT/R and DEN
are provided by the 8086.
A write cycle also begins with the assertion of ALE
and the emission of the address. The M/IO signal is
again asserted to indicate a memory or I/O write
operation. In the T2 immediately following the address
emission the processor emits the data to be
written into the addressed location. This data remains
valid until the middle of T4. During T2, T3, and
TW the processor asserts the write control signal.
The write (WR) signal becomes active at the beginning
of T2 as opposed to the read which is delayed
somewhat into T2 to provide time for the bus to float.
The BHE and A0 signals are used to select the proper
byte(s) of the memory/IO word to be read or written
according to the following table:
BHE A0 Characteristics
0 0 Whole word
0 1 Upper byte from/to
odd address
1 0 Lower byte from/to
even address
1 1 None
I/O ports are addressed in the same manner as
memory location. Even addressed bytes are transferred
on the D7±D0 bus lines and odd addressed
bytes on D15±D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
signal (INTA) is asserted in place of the
read (RD) signal and the address bus is floated.
(See Figure 6.) In the second of two successive
INTA cycles, a byte of information is read from bus
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8086
lines D7±D0 as supplied by the inerrupt system logic
(i.e., 8259A Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied
by four and used as a pointer into an interrupt
vector lookup table, as described earlier.
BUS TIMINGÐMEDIUM SIZE SYSTEMS
For medium size systems the MN/MX pin is connected
to VSS and the 8288 Bus Controller is added
to the system as well as a latch for latching the system
address, and a transceiver to allow for bus loading
greater than the 8086 is capable of handling.
Signals ALE, DEN, and DT/R are generated by the
8288 instead of the processor in this configuration
although their timing remains relatively the same.
The 8086 status outputs (S2, S1 , and S0) provide
type-of-cycle information and become 8288 inputs.
This bus cycle information specifies read (code,
data, or I/O), write (data or I/O), interrupt
acknowledge, or software halt. The 8288 thus issues
control signals specifying memory read or write, I/O
read or write, or interrupt acknowledge. The 8288
provides two types of write strobes, normal and advanced,
to be applied as required. The normal write
strobes have data valid at the leading edge of write.
The advanced write strobes have the same timing
as read strobes, and hence data isn't valid at the
leading edge of write. The transceiver receives the
usual DIR and G inputs from the 8288's DT/R and
DEN.
The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive
from an 8259A located on either the local bus or the
system bus. If the master 8259A Priority Interrupt
Controller is positioned on the local bus, a TTL gate
is required to disable the transceiver when reading
from the master 8259A during the interrupt acknowledge
sequence and software ``poll''.
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8086
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ÀÀÀÀÀÀ0§C to 70§C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§C to a150§C
Voltage on Any Pin with
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀb1.0V to a7V
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5W
NOTICE: This is a production data sheet. The specifications
are subject to change without notice.
*WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and extended
exposure beyond the ``Operating Conditions''
may affect device reliability.
D.C. CHARACTERISTICS (8086: TA e 0§C to 70§C, VCC e 5V g10%)
(8086-1: TA e 0§C to 70§C, VCC e 5V g5%)
(8086-2: TA e 0§C to 70§C, VCC e 5V g5%)
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage b0.5 a0.8 V (Note 1)
VIH Input High Voltage 2.0 VCC a 0.5 V (Notes 1, 2)
VOL Output Low Voltage 0.45 V IOL e 2.5 mA
VOH Output High Voltage 2.4 V IOHe b400 mA
ICC Power Supply Current: 8086 340
8086-1 360 mA TA e 25§C
8086-2 350
ILI Input Leakage Current g10 mA 0VsVIN s VCC (Note 3)
ILO Output Leakage Current g10 mA 0.45V s VOUT s VCC
VCL Clock Input Low Voltage b0.5 a0.6 V
VCH Clock Input High Voltage 3.9 VCC a 1.0 V
CIN Capacitance of Input Buffer 15 pF fc e 1 MHz
(All input except
AD0±AD15, RQ/GT)
CIO Capacitance of I/O Buffer 15 pF fc e 1 MHz
(AD0±AD15, RQ/GT)
NOTES:
1. VIL tested with MN/MX Pin e 0V. VIH tested with MN/MX Pin e 5V. MN/MX Pin is a Strap Pin.
2. Not applicable to RQ/GT0 and RQ/GT1 (Pins 30 and 31).
3. HOLD and HLDA ILI min e 30 mA, max e 500 mA.
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8086
A.C. CHARACTERISTICS (8086: TA e 0§C to 70§C, VCC e 5V g 10%)
(8086-1: TA e 0§C to 70§C, VCC e 5V g 5%)
(8086-2: TA e 0§C to 70§C, VCC e 5V g 5%)
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
Symbol Parameter
8086 8086-1 8086-2
Units Test Conditions
Min Max Min Max Min Max
TCLCL CLK Cycle Period 200 500 100 500 125 500 ns
TCLCH CLK Low Time 118 53 68 ns
TCHCL CLK High Time 69 39 44 ns
TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V
TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.0V
TDVCL Data in Setup Time 30 5 20 ns
TCLDX Data in Hold Time 10 10 10 ns
TR1VCL RDY Setup Time 35 35 35 ns
into 8284A (See
Notes 1, 2)
TCLR1X RDY Hold Time 0 0 0 ns
into 8284A (See
Notes 1, 2)
TRYHCH READY Setup 118 53 68 ns
Time into 8086
TCHRYX READY Hold Time 30 20 20 ns
into 8086
TRYLCL READY Inactive to b8 b10 b8 ns
CLK (See Note 3)
THVCH HOLD Setup Time 35 20 20 ns
TINVCH INTR, NMI, TEST 30 15 15 ns
Setup Time (See
Note 2)
TILIH Input Rise Time 20 20 20 ns From 0.8V to 2.0V
(Except CLK)
TIHIL Input Fall Time 12 12 12 ns From 2.0V to 0.8V
(Except CLK)
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A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol Parameter
8086 8086-1 8086-2
Units Test
Min Max Min Max Min Max Conditions
TCLAV Address Valid Delay 10 110 10 50 10 60 ns
TCLAX Address Hold Time 10 10 10 ns
TCLAZ Address Float TCLAX 80 10 40 TCLAX 50 ns
Delay
TLHLL ALE Width TCLCH-20 TCLCH-10 TCLCH-10 ns
TCLLH ALE Active Delay 80 40 50 ns
TCHLL ALE Inactive Delay 85 45 55 ns
TLLAX Address Hold Time TCHCL-10 TCHCL-10 TCHCL-10 ns
TCLDV Data Valid Delay 10 110 10 50 10 60 ns *CL e 20±100 pF
for all 8086
TCHDX Data Hold Time 10 10 10 ns
Outputs (In
TWHDX Data Hold Time TCLCH-30 TCLCH-25 TCLCH-30 ns addition to 8086
After WR selfload)
TCVCTV Control Active 10 110 10 50 10 70 ns
Delay 1
TCHCTV Control Active 10 110 10 45 10 60 ns
Delay 2
TCVCTX Control Inactive 10 110 10 50 10 70 ns
Delay
TAZRL Address Float to 0 0 0 ns
READ Active
TCLRL RD Active Delay 10 165 10 70 10 100 ns
TCLRH RD Inactive Delay 10 150 10 60 10 80 ns
TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns
Address Active
TCLHAV HLDA Valid Delay 10 160 10 60 10 100 ns
TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns
TWLWH WR Width 2TCLCL-60 2TCLCL-35 2TCLCL-40 ns
TAVAL Address Valid to TCLCH-60 TCLCH-35 TCLCH-40 ns
ALE Low
TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V
TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V
NOTES:
1. Signal at 8284A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state. (8 ns into T3).
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8086
A.C. TESTING INPUT, OUTPUT WAVEFORM
231455-11
A.C. Testing: Inputs are driven at 2.4V for a Logic ``1'' and 0.45V
for a Logic ``0''. Timing measurements are made at 1.5V for both
a Logic ``1'' and ``0''.
A.C. TESTING LOAD CIRCUIT
231455±12
CL Includes Jig Capacitance
WAVEFORMS
MINIMUM MODE
231455±13
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WAVEFORMS (Continued)
MINIMUM MODE (Continued)
231455±14
SOFTWARE HALTÐ
RD, WR, INTA e VOH
DT/R e INDETERMINATE
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control
signals shown for second INTA cycle.
4. Signals at 8284A are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
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A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol Parameter
8086 8086-1 8086-2
Units Test
Min Max Min Max Min Max Conditions
TCLCL CLK Cycle Period 200 500 100 500 125 500 ns
TCLCH CLK Low Time 118 53 68 ns
TCHCL CLK High Time 69 39 44 ns
TCH1CH2 CLK Rise Time 10 10 10 ns From 1.0V to 3.5V
TCL2CL1 CLK Fall Time 10 10 10 ns From 3.5V to 1.0V
TDVCL Data in Setup Time 30 5 20 ns
TCLDX Data in Hold Time 10 10 10 ns
TR1VCL RDY Setup Time 35 35 35 ns
into 8284A
(Notes 1, 2)
TCLR1X RDY Hold Time 0 0 0 ns
into 8284A
(Notes 1, 2)
TRYHCH READY Setup 118 53 68 ns
Time into 8086
TCHRYX READY Hold Time 30 20 20 ns
into 8086
TRYLCL READY Inactive to b8 b10 b8 ns
CLK (Note 4)
TINVCH Setup Time for 30 15 15 ns
Recognition (INTR,
NMI, TEST)
(Note 2)
TGVCH RQ/GT Setup Time 30 15 15 ns
(Note 5)
TCHGX RQ Hold Time into 40 20 30 ns
8086
TILIH Input Rise Time 20 20 20 ns From 0.8V to 2.0V
(Except CLK)
TIHIL Input Fall Time 12 12 12 ns From 2.0V to 0.8V
(Except CLK)
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A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol Parameter
8086 8086-1 8086-2
Units Test
Min Max Min Max Min Max Conditions
TCLML Command Active 10 35 10 35 10 35 ns
Delay (See Note 1)
TCLMH Command Inactive 10 35 10 35 10 35 ns
Delay (See Note 1)
TRYHSH READY Active to 110 45 65 ns
Status Passive (See
Note 3)
TCHSV Status Active Delay 10 110 10 45 10 60 ns
TCLSH Status Inactive 10 130 10 55 10 70 ns
Delay
TCLAV Address Valid Delay 10 110 10 50 10 60 ns
TCLAX Address Hold Time 10 10 10 ns
TCLAZ Address Float Delay TCLAX 80 10 40 TCLAX 50 ns
TSVLH Status Valid to ALE 15 15 15 ns
High (See Note 1)
TSVMCH Status Valid to 15 15 15 ns
MCE High (See
Note 1)
TCLLH CLK Low to ALE 15 15 15 ns CL e 20±100 pF
Valid (See Note 1) for all 8086
Outputs (In
TCLMCH CLK Low to MCE 15 15 15 ns addition to 8086
High (See Note 1) self-load)
TCHLL ALE Inactive Delay 15 15 15 ns
(See Note 1)
TCLMCL MCE Inactive Delay 15 15 15 ns
(See Note 1)
TCLDV Data Valid Delay 10 110 10 50 10 60 ns
TCHDX Data Hold Time 10 10 10 ns
TCVNV Control Active 5 45 5 45 5 45 ns
Delay (See Note 1)
TCVNX Control Inactive 10 45 10 45 10 45 ns
Delay (See Note 1)
TAZRL Address Float to 0 0 0 ns
READ Active
TCLRL RD Active Delay 10 165 10 70 10 100 ns
TCLRH RD Inactive Delay 10 150 10 60 10 80 ns
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8086
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES (Continued)
Symbol Parameter
8086 8086-1 8086-2
Units Test
Min Max Min Max Min Max Conditions
TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns
Address Active
TCHDTL Direction Control 50 50 50 ns CL e 20±100 pF
Active Delay for all 8086
(Note 1) Outputs (In
addition to 8086
TCHDTH Direction Control 30 30 30 ns self-load)
Inactive Delay
(Note 1)
TCLGL GT Active Delay 0 85 0 38 0 50 ns
TCLGH GT Inactive Delay 0 85 0 45 0 50 ns
TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns
TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V
TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T3 and wait states.
4. Applies only to T2 state (8 ns into T3).
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WAVEFORMS
MAXIMUM MODE
231455±15
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8086
WAVEFORMS (Continued)
MAXIMUM MODE (Continued)
231455±16
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for
pointer address is shown for second INTA cycle.
5. Signals at 8284A or 8288 are shown for reference only.
6. The issuance of the 8288 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN)
lags the active high 8288 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T4.
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8086
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
231455±17
NOTE:
1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
231455±18
RESET TIMING
231455±19
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
231455±20
NOTE:
The coprocessor may not drive the buses outside the region shown without risking contention.
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8086
WAVEFORMS (Continued)
HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
231455±21
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8086
Table 2. Instruction Set Summary
Mnemonic and
Instruction Code
Description
DATA TRANSFER
MOV e Move: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Register/Memory to/from Register 1 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w e 1
Immediate to Register 1 0 1 1 w reg data data if w e 1
Memory to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high
Accumulator to Memory 1 0 1 0 0 0 1 w addr-low addr-high
Register/Memory to Segment Register 1 0 0 0 1 1 1 0 mod 0 reg r/m
Segment Register to Register/Memory 1 0 0 0 1 1 0 0 mod 0 reg r/m
PUSH e Push:
Register/Memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP e Pop:
Register/Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m
Register 0 1 0 1 1 reg
Segment Register 0 0 0 reg 1 1 1
XCHG e Exchange:
Register/Memory with Register 1 0 0 0 0 1 1 w mod reg r/m
Register with Accumulator 1 0 0 1 0 reg
IN e Input from:
Fixed Port 1 1 1 0 0 1 0 w port
Variable Port 1 1 1 0 1 1 0 w
OUT e Output to:
Fixed Port 1 1 1 0 0 1 1 w port
Variable Port 1 1 1 0 1 1 1 w
XLAT e Translate Byte to AL 1 1 0 1 0 1 1 1
LEA e Load EA to Register 1 0 0 0 1 1 0 1 mod reg r/m
LDS e Load Pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m
LES e Load Pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m
LAHF e Load AH with Flags 1 0 0 1 1 1 1 1
SAHF e Store AH into Flags 1 0 0 1 1 1 1 0
PUSHF e Push Flags 1 0 0 1 1 1 0 0
POPF e Pop Flags 1 0 0 1 1 1 0 1
Mnemonics © Intel, 1978
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8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
ARITHMETIC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ADD e Add:
Reg./Memory with Register to Either 0 0 0 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s: w e 01
Immediate to Accumulator 0 0 0 0 0 1 0 w data data if w e 1
ADC e Add with Carry:
Reg./Memory with Register to Either 0 0 0 1 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s: w e 01
Immediate to Accumulator 0 0 0 1 0 1 0 w data data if w e 1
INC e Increment:
Register/Memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA e ASCII Adjust for Add 0 0 1 1 0 1 1 1
BAA e Decimal Adjust for Add 0 0 1 0 0 1 1 1
SUB e Subtract:
Reg./Memory and Register to Either 0 0 1 0 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s w e 01
Immediate from Accumulator 0 0 1 0 1 1 0 w data data if w e 1
SSB e Subtract with Borrow
Reg./Memory and Register to Either 0 0 0 1 1 0 d w mod reg r/m
Immediate from Register/Memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s w e 01
Immediate from Accumulator 0 0 0 1 1 1 w data data if w e 1
DEC e Decrement:
Register/memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG e Change sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m
CMP e Compare:
Register/Memory and Register 0 0 1 1 1 0 d w mod reg r/m
Immediate with Register/Memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s w e 01
Immediate with Accumulator 0 0 1 1 1 1 0 w data data if w e 1
AAS e ASCII Adjust for Subtract 0 0 1 1 1 1 1 1
DAS e Decimal Adjust for Subtract 0 0 1 0 1 1 1 1
MUL e Multiply (Unsigned) 1 1 1 1 0 1 1 w mod 1 0 0 r/m
IMUL e Integer Multiply (Signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m
AAM e ASCII Adjust for Multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0
DIV e Divide (Unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m
IDIV e Integer Divide (Signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m
AAD e ASCII Adjust for Divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0
CBW e Convert Byte to Word 1 0 0 1 1 0 0 0
CWD e Convert Word to Double Word 1 0 0 1 1 0 0 1
Mnemonics © Intel, 1978
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Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
LOGIC 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
NOT e Invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m
SHL/SAL e Shift Logical/Arithmetic Left 1 1 0 1 0 0 v w mod 1 0 0 r/m
SHR e Shift Logical Right 1 1 0 1 0 0 v w mod 1 0 1 r/m
SAR e Shift Arithmetic Right 1 1 0 1 0 0 v w mod 1 1 1 r/m
ROL e Rotate Left 1 1 0 1 0 0 v w mod 0 0 0 r/m
ROR e Rotate Right 1 1 0 1 0 0 v w mod 0 0 1 r/m
RCL e Rotate Through Carry Flag Left 1 1 0 1 0 0 v w mod 0 1 0 r/m
RCR e Rotate Through Carry Right 1 1 0 1 0 0 v w mod 0 1 1 r/m
AND e And:
Reg./Memory and Register to Either 0 0 1 0 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w e 1
Immediate to Accumulator 0 0 1 0 0 1 0 w data data if w e 1
TEST e And Function to Flags, No Result:
Register/Memory and Register 1 0 0 0 0 1 0 w mod reg r/m
Immediate Data and Register/Memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w e 1
Immediate Data and Accumulator 1 0 1 0 1 0 0 w data data if w e 1
OR e Or:
Reg./Memory and Register to Either 0 0 0 0 1 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 0 0 1 r/m data data if w e 1
Immediate to Accumulator 0 0 0 0 1 1 0 w data data if w e 1
XOR e Exclusive or:
Reg./Memory and Register to Either 0 0 1 1 0 0 d w mod reg r/m
Immediate to Register/Memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w e 1
Immediate to Accumulator 0 0 1 1 0 1 0 w data data if w e 1
STRING MANIPULATION
REP e Repeat 1 1 1 1 0 0 1 z
MOVS e Move Byte/Word 1 0 1 0 0 1 0 w
CMPS e Compare Byte/Word 1 0 1 0 0 1 1 w
SCAS e Scan Byte/Word 1 0 1 0 1 1 1 w
LODS e Load Byte/Wd to AL/AX 1 0 1 0 1 1 0 w
STOS e Stor Byte/Wd from AL/A 1 0 1 0 1 0 1 w
CONTROL TRANSFER
CALL e Call:
Direct within Segment 1 1 1 0 1 0 0 0 disp-low disp-high
Indirect within Segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m
Direct Intersegment 1 0 0 1 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m
Mnemonics © Intel, 1978
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8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
JMP e Unconditional Jump: 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Direct within Segment 1 1 1 0 1 0 0 1 disp-low disp-high
Direct within Segment-Short 1 1 1 0 1 0 1 1 disp
Indirect within Segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m
Direct Intersegment 1 1 1 0 1 0 1 0 offset-low offset-high
seg-low seg-high
Indirect Intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m
RET e Return from CALL:
Within Segment 1 1 0 0 0 0 1 1
Within Seg Adding Immed to SP 1 1 0 0 0 0 1 0 data-low data-high
Intersegment 1 1 0 0 1 0 1 1
Intersegment Adding Immediate to SP 1 1 0 0 1 0 1 0 data-low data-high
JE/JZ e Jump on Equal/Zero 0 1 1 1 0 1 0 0 disp
JL/JNGE e Jump on Less/Not Greater 0 1 1 1 1 1 0 0 disp
or Equal
JLE/JNG e Jump on Less or Equal/ 0 1 1 1 1 1 1 0 disp
Not Greater
JB/JNAE e Jump on Below/Not Above 0 1 1 1 0 0 1 0 disp
or Equal
JBE/JNA e Jump on Below or Equal/ 0 1 1 1 0 1 1 0 disp
Not Above
JP/JPE e Jump on Parity/Parity Even 0 1 1 1 1 0 1 0 disp
JO e Jump on Overflow 0 1 1 1 0 0 0 0 disp
JS e Jump on Sign 0 1 1 1 1 0 0 0 disp
JNE/JNZ e Jump on Not Equal/Not Zero 0 1 1 1 0 1 0 1 disp
JNL/JGE e Jump on Not Less/Greater 0 1 1 1 1 1 0 1 disp
or Equal
JNLE/JG e Jump on Not Less or Equal/ 0 1 1 1 1 1 1 1 disp
Greater
JNB/JAE e Jump on Not Below/Above 0 1 1 1 0 0 1 1 disp
or Equal
JNBE/JA e Jump on Not Below or 0 1 1 1 0 1 1 1 disp
Equal/Above
JNP/JPO e Jump on Not Par/Par Odd 0 1 1 1 1 0 1 1 disp
JNO e Jump on Not Overflow 0 1 1 1 0 0 0 1 disp
JNS e Jump on Not Sign 0 1 1 1 1 0 0 1 disp
LOOP e Loop CX Times 1 1 1 0 0 0 1 0 disp
LOOPZ/LOOPE e Loop While Zero/Equal 1 1 1 0 0 0 0 1 disp
LOOPNZ/LOOPNE e Loop While Not 1 1 1 0 0 0 0 0 disp
Zero/Equal
JCXZ e Jump on CX Zero 1 1 1 0 0 0 1 1 disp
INT e Interrupt
Type Specified 1 1 0 0 1 1 0 1 type
Type 3 1 1 0 0 1 1 0 0
INTO e Interrupt on Overflow 1 1 0 0 1 1 1 0
IRET e Interrupt Return 1 1 0 0 1 1 1 1
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8086
Table 2. Instruction Set Summary (Continued)
Mnemonic and
Instruction Code
Description
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PROCESSOR CONTROL
CLC e Clear Carry 1 1 1 1 1 0 0 0
CMC e Complement Carry 1 1 1 1 0 1 0 1
STC e Set Carry 1 1 1 1 1 0 0 1
CLD e Clear Direction 1 1 1 1 1 1 0 0
STD e Set Direction 1 1 1 1 1 1 0 1
CLI e Clear Interrupt 1 1 1 1 1 0 1 0
STI e Set Interrupt 1 1 1 1 1 0 1 1
HLT e Halt 1 1 1 1 0 1 0 0
WAIT e Wait 1 0 0 1 1 0 1 1
ESC e Escape (to External Device) 1 1 0 1 1 x x x mod x x x r/m
LOCK e Bus Lock Prefix 1 1 1 1 0 0 0 0
NOTES:
AL e 8-bit accumulator
AX e 16-bit accumulator
CX e Count register
DS e Data segment
ES e Extra segment
Above/below refers to unsigned value
Greater e more positive;
Less e less positive (more negative) signed values
if d e 1 then ``to'' reg; if d e 0 then ``from'' reg
if w e 1 then word instruction; if w e 0 then byte instruction
if mod e 11 then r/m is treated as a REG field
if mod e 00 then DISP e 0*, disp-low and disp-high are
absent
if mod e 01 then DISP e disp-low sign-extended to
16 bits, disp-high is absent
if mod e 10 then DISP e disp-high; disp-low
if r/m e 000 then EA e (BX) a (SI) a DISP
if r/m e 001 then EA e (BX) a (DI) a DISP
if r/m e 010 then EA e (BP) a (SI) a DISP
if r/m e 011 then EA e (BP) a (DI) a DISP
if r/m e 100 then EA e (SI) a DISP
if r/m e 101 then EA e (DI) a DISP
if r/m e 110 then EA e (BP) a DISP*
if r/m e 111 then EA e (BX) a DISP
DISP follows 2nd byte of instruction (before data if required)
*except if mod e 00 and r/m e 110 then EA e disp-high;
disp-low.
Mnemonics © Intel, 1978
if s w e 01 then 16 bits of immediate data form the operand
if s w e 11 then an immediate data byte is sign extended
to form the 16-bit operand
if v e 0 then ``count'' e 1; if v e 1 then ``count'' in (CL)
x e don't care
z is used for string primitives for comparison with ZF FLAG
SEGMENT OVERRIDE PREFIX
0 0 1 reg 1 1 0
REG is assigned according to the following table:
16-Bit (w e 1) 8-Bit (w e 0) Segment
000 AX 000 AL 00 ES
001 CX 001 CL 01 CS
010 DX 010 DL 10 SS
011 BX 011 BL 11 DS
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
Instructions which reference the flag register file as a 16-bit
object use the symbol FLAGS to represent the file:
FLAGS e X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
DATA SHEET REVISION REVIEW
The following list represents key differences between this and the -004 data sheet. Please review this summary
carefully.
1. The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III).
2. Delete all ``changes from 1985 Handbook Specification'' sentences.
30
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February 1990 Order Number: 271103-001
M80C286
HIGH PERFORMANCE CHMOS MICROPROCESSOR
WITH MEMORY MANAGEMENT AND PROTECTION
Military
Y High Speed CHMOS III Technology
Y Pin for Pin, Clock for Clock, and
Functionally Compatible with the HMOS
M80286
(See M80286 Data Sheet, Order Ý271028-003)
Y Stop Clock Capability
ÐUses Less Power (see ICCS
Specification)
Y 10 MHz Clock Rate
Y 68 Lead Pin Grid Array Package
Y 68 Lead Ceramic Quad Flatpack
Package
(See Packaging Spec., Order Ý231369)
Y Military Temperature Range:
b55§C to a125§C (TC)
INTRODUCTION
The M80C286 is an advanced 16 bit CHMOS III microprocessor designed for multi-user and multi-tasking
applications that require low power and high performance. The M80C286 is fully compatible with its predecessor
the HMOS M80286 and object-code compatible with the M8086 and M80386 family of products. In
addition, the M80C286 has a power down mode which uses less power, making it ideal for mobile applications.
The M80C286 has built-in memory protection that maintains a four level protection mechanism for task isolation,
a hardware task switching facility and memory mangement capabilities that map 230 bytes (one gigabyte)
of virtual address space per task (per user) into 224 bytes (16 megabytes) of physical memory.
The M80C286 is upward compatible with M8086 and M8088 software. Using M8086 real address mode, the
M80C286 is object code compatible with existing M8086, M8088 software. In protected virtual address mode,
the M80C286 is source code compatible with M8086, M8088 software which may require upgrading to use
virtual addresses supported by the M80C286's integrated memory management and protection mechanism.
Both modes operate at full M80C286 performance and execute a superset of the M8086 and M8088 instructions.
The M80C286 provides special operations to support the efficient implementation and execution of operating
systems. For example, one instruction can end execution of one task, save its state, switch to a new task, load
its state, and start execution of the new task. The M80C286 also supports virtual memory systems by providing
a segment-not-present exception and restartable instructions.
271103±1
Figure 1. M80C286 Internal Block Diagram
M80C286
FUNCTIONAL DESCRIPTION
Introduction
The M80C286 is an advanced, high-performance microprocessor
with specially optimized capabilities for
multiple user and multi-tasking systems. Depending
on the application, a 10 MHz M80C286's performance
is up to eight times faster than the standard 5
MHz M8086's, while providing complete upward
software compatibility with Intel's M8086, 88, and
186 family of CPU's.
The M80C286 operates in two modes: M8086 real
address mode and protected virtual address mode.
Both modes execute a superset of the M8086 and
88 instruction set.
In M8086 real address mode programs use real addresses
with up to one megabyte of address space.
Programs use virtual addresses in protected virtual
address mode, also called protected mode. In protected
mode, the M80C286 CPU automatically maps
1 gigabyte of virtual addresses per task into a 16
megabyte real address space. This mode also provides
memory protection to isolate the operating
system and ensure privacy of each tasks' programs
and data. Both modes provide the same base instruction
set, registers, and addressing modes.
The following Functional Description describes first,
the base M80C286 architecture common to both
modes, second, M8086 real address mode, and
third, protected mode.
M80C286 BASE ARCHITECTURE
The M8086, 88, 186, and 286 CPU family all contain
the same basic set of registers, instructions, and
addressing modes. The M80C286 processor is upward
compatible with the M8086, M8088, and 80186
CPU's and fully compatible with the HMOS M80286.
Register Set
The M80C286 base architecture has fifteen registers
as shown in Figure 2. These registers are grouped
into the following four categories:
General Registers: Eight 16-bit general purpose
registers used to contain arithmetic and logical operands.
Four of these (AX, BX, CX, and DX) can be
used either in their entirety as 16-bit words or split
into pairs of separate 8-bit registers.
Segment Registers: Four 16-bit special purpose
registers select, at any given time, the segments of
memory that are immediately addressable for code,
stack, and data. (For usage, refer to Memory Organization.)
Base and Index Registers: Four of the general purpose
registers may also be used to determine offset
addresses of operands in memory. These registers
may contain base addresses or indexes to particular
locations within a segment. The addressing mode
determines the specific registers used for operand
address calculations.
Status and Control Registers: The 3 16-bit special
purpose registers in Figure 3 record or control certain
aspects of the M80C286 processor state including
the Instruction Pointer, which contains the offset
address of the next sequential instruction to be executed.
16-BIT SPECIAL
REGISTER REGISTER
NAME FUNCTIONS
7 0 7 0
BYTE
ADDRESSABLE
AX AH AL
MULTIPLY/DIVIDE
REGISTER
(8-BIT DX DH DL
I/O INSTRUCTIONS *
SHOWN)
NAMES
CX CH CL ( LOOP/SHIFT/REPEAT/COUNT %BX BH BL
BASE REGISTERS
BP *
SI
INDEX REGISTERS
DI *
SP ( STACK POINTER
15 0
GENERAL
REGISTERS
15 0
CS CODE SEGMENT SELECTOR
DS DATA SEGMENT SELECTOR
SS STACK SEGMENT SELECTOR
ES EXTRA SEGMENT SELECTOR
SEGMENT REGISTERS
15 0
F STATUS WORD
IP INSTRUCTION POINTER
STATUS AND CONTROL
REGISTERS
Figure 2. Register Set
2
M80C286
271103±2
Figure 3. Status and Control Register Bit Functions
Flags Word Description
The Flags word (Flags) records specific characteristics
of the result of logical and arithmetic instructions
(bits 0, 2, 4, 6, 7, and 11) and controls the operation
of the M80C286 within a given operating mode (bits
8 and 9). Flags is a 16-bit register. The function of
the flag bits is given in Table 1.
Instruction Set
The instruction set is divided into seven categories:
data transfer, arithmetic, shift/rotate/logical, string
manipulation, control transfer, high level instructions,
and processor control. These categories are
summarized in Table 2.
An M80C286 instruction can reference zero, one, or
two operands; where an operand resides in a register,
in the instruction itself, or in memory. Zero-operand
instructions (e.g. NOP and HLT) are usually one
byte long. One-operand instructions (e.g. INC and
DEC) are usually two bytes long but some are encoded
in only one byte. One-operand instructions
may reference a register or memory location. Twooperand
instructions permit the following six types of
instruction operations:
ÐRegister to Register
ÐMemory to Register
ÐImmediate to Register
ÐMemory to Memory
ÐRegister to Memory
ÐImmediate to Memory
Table 1. Flags Word Bit Functions
Bit
Name Function
Position
0 CF Carry FlagÐSet on high-order bit
carry or borrow; cleared otherwise
2 PF Parity FlagÐSet if low-order 8 bits
of result contain an even number of
1-bits; cleared otherwise
4 AF Set on carry from or borrow to the
low order four bits of AL; cleared
otherwise
6 ZF Zero FlagÐSet if result is zero;
cleared otherwise
7 SF Sign FlagÐSet equal to high-order
bit of result (0 if positive, 1 if negative)
11 OF Overflow FlagÐSet if result is a toolarge
positive number or a too-small
negative number (excluding sign-bit)
to fit in destination operand; cleared
otherwise
8 TF Single Step FlagÐOnce set, a single
step interrupt occurs after the
next instruction executes. TF is
cleared by the single step interrupt.
9 IF Interrupt-enable FlagÐWhen set,
maskable interrupts will cause the
CPU to transfer control to an interrupt
vector specified location.
10 DF Direction FlagÐCauses string
instructions to auto decrement
the appropriate index registers
when set. Clearing DF causes
auto increment.
3
M80C286
Two-operand instructions (e.g. MOV and ADD) are
usually three to six bytes long. Memory to memory
operations are provided by a special class of string
instructions requiring one to three bytes. For detailed
instruction formats and encodings refer to the
instruction set summary at the end of this document.
For detailed operation and usage of each instruction,
see Appendix B of the 80286/80287 Programmer's
Reference Manual (Order No. 210498).
Table 2. Instruction Set
GENERAL PURPOSE
MOV Move byte or word
PUSH Push word onto stack
POP Pop word off stack
PUSHA Push all registers on stack
POPA Pop all registers from stack
XCHG Exchange byte or word
XLAT Translate byte
INPUT/OUTPUT
IN Input byte or word
OUT Output byte or word
ADDRESS OBJECT
LEA Load effective address
LDS Load pointer using DS
LES Load pointer using ES
FLAG TRANSFER
LAHF Load AH register from flags
SAHF Store AH register in flags
PUSHF Push flags onto stack
POPF Pop flags off stack
Data Transfer Instructions
MOVS Move byte or word string
INS Input bytes or word string
OUTS Output bytes or word string
CMPS Compare byte or word string
SCAS Scan byte or word string
LODS Load byte or word string
STOS Store byte or word string
REP Repeat
REPE/REPZ Repeat while equal/zero
REPNE/REPNZ Repeat while not equal/not zero
String Instructions
ADDITION
ADD Add byte or word
ADC Add byte or word with carry
INC Increment byte or word by 1
AAA ASCII adjust for addition
DAA Decimal adjust for addition
SUBTRACTION
SUB Subtract byte or word
SBB Subtract byte or word with borrow
DEC Decrement byte or word by 1
NEG Negate byte or word
CMP Compare byte or word
AAS ASCII adjust for subtraction
DAS Decimal adjust for subtraction
MULTIPLICATION
MUL Multiple byte or word unsigned
IMUL Integer multiply byte or word
AAM ASCII adjust for multiply
DIVISION
DIV Divide byte or word unsigned
IDIV Integer divide byte or word
AAD ASCII adjust for division
CBW Convert byte to word
CWD Convert word to doubleword
Arithmetic Instructions
LOGICALS
NOT ``Not'' byte or word
AND ``And'' byte or word
OR ``Inclusive or'' byte or word
XOR ``Exclusive or'' byte or word
TEST ``Test'' byte or word
SHIFTS
SHL/SAL Shift logical/arithmetic left byte or word
SHR Shift logical right byte or word
SAR Shift arithmetic right byte or word
ROTATES
ROL Rotate left byte or word
ROR Rotate right byte or word
RCL Rotate through carry left byte or word
RCR Rotate through carry right byte or word
Shift/Rotate Logical Instructions
4
M80C286
Table 2. Instruction Set (Continued)
CONDITIONAL TRANSFERS
JA/JNBE Jump if above/not below nor equal
JAE/JNB Jump if above or equal/not below
JB/JNAE Jump if below/not above nor equal
JBE/JNA Jump if below or equal/not above
JC Jump if carry
JE/JZ Jump if equal/zero
JG/JNLE Jump if greater/not less nor equal
JGE/JNL Jump if greater or equal/not less
JL/JNGE Jump if less/not greater nor equal
JLE/JNG Jump if less or equal/not greater
JNC Jump if not carry
JNE/JNZ Jump if not equal/not zero
JNO Jump if not overflow
JNP/JPO Jump if not parity/parity odd
JNS Jump if not sign
JO Jump if overflow
JP/JPE Jump if parity/parity even
JS Jump if sign
UNCONDITIONAL TRANSFERS
CALL Call procedure
RET Return from procedure
JMP Jump
ITERATION CONTROLS
LOOP Loop
LOOPE/LOOPZ Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/not zero
JCXZ Jump if register CX e 0
INTERRUPTS
INT Interrupt
INTO Interrupt if overflow
IRET Interrupt return
Program Transfer Instructions
FLAG OPERATIONS
STC Set carry flag
CLC Clear carry flag
CMC Complement carry flag
STD Set direction flag
CLD Clear direction flag
STI Set interrupt enable flag
CLI Clear interrupt enable flag
EXTERNAL SYNCHRONIZATION
HLT Halt until interrupt or reset
WAIT Wait for BUSY not active
ESC Escape to extension processor
LOCK Lock bus during next instruction
NO OPERATION
NOP No operation
EXECUTION ENVIRONMENT CONTROL
LMSW Load machine status word
SMSW Store machine status word
Process Control Instructions
ENTER Format stack for procedure entry
LEAVE Restore stack for procedure exit
BOUND Detects values outside
prescribed range
High Level Instructions
Memory Organization
Memory is organized as sets of variable length segments.
Each segment is a linear contiguous sequence
of up to 64K (216) 8-bit bytes. Memory is
addressed using a two component address (a pointer)
that consists of a 16-bit segment selector, and a
16-bit offset, see Figure 4. The segment selector indicates
the desired segment in memory. The offset
component indicates the desired byte address within
the segment.
271103±3
Figure 4. Two Component Address
5
M80C286
Table 3. Segment Register Selection Rules
Memory Segment Register Implicit Segment
Reference Needed Used Selection Rule
Instructions Code (CS) Automatic with instruction prefetch
Stack Stack (SS) All stack pushes and pops. Any memory reference which uses BP
as a base register.
Local Data Data (DS) All data references except when relative to stack or
string destination
External (Global) Data Extra (ES) Alternate data segment and destination of string operation
All instructions that address operands in memory
must specify the segment and the offset. For speed
and compact instruction encoding, segment selectors
are usually stored in the high speed segment
registers. An instruction need specify only the desired
segment register and an offset in order to address
a memory operand.
Most instructions need not explicitly specify which
segment register is used. The correct segment register
is automatically chosen according to the rules
of Table 3. These rules follow the way programs are
written (see Figure 5) as independent modules that
require areas for code and data, a stack, and access
to external data areas.
Special segment override instruction prefixes allow
the implicit segment register selection rules to be
overridden for special cases. The stack, data, and
extra segments may coincide for simple programs.
To access operands not residing in one of the four
immediately available segments, a full 32-bit pointer
or a new segment selector must be loaded.
Addressing Modes
The M80C286 provides a total of eight addressing
modes for instructions to specify operands. Two addressing
modes are provided for instructions that
operate on register or immediate operands:
Register Operand Mode: The operand is located
in one of the 8 or 16-bit general registers.
Immediate Operand Mode: The operand is included
in the instruction.
Six modes are provided to specify the location of an
operand in a memory segment. A memory operand
address consists of two 16-bit components: segment
selector and offset. The segment selector is
supplied by a segment register either implicitly chosen
by the addressing mode or explicitly chosen by
a segment override prefix. The offset is calculated
by summing any combination of the following three
address elements:
the displacement (an 8 or 16-bit immediate value
contained in the instruction)
the base (contents of either the BX or BP base
registers)
271103±4
Figure 5. Segmented Memory Helps
Structure Software
the index (contents of either the SI or DI index
registers)
Any carry out from the 16-bit addition is ignored.
Eight-bit displacements are sign extended to 16-bit
values.
Combinations of these three address elements define
the six memory addressing modes, described
below.
Direct Mode: The operand's offset is contained in
the instruction as an 8 or 16-bit displacement element.
Register Indirect Mode: The operand's offset is in
one of the registers SI, DI, BX, or BP.
Based Mode: The operand's offset is the sum of an
8 or 16-bit displacement and the contents of a base
register (BX or BP).
6
M80C286
Indexed Mode: The operand's offset is the sum of
an 8 or 16-bit displacement and the contents of an
index register (SI or DI).
Based Indexed Mode: The operand's offset is the
sum of the contents of a base register and an index
register.
Based Indexed Mode with Displacement: The operand's
offset is the sum of a base register's contents,
an index register's contents, and an 8 or 16-bit
displacement.
Data Types
The M80C286 directly supports the following data
types:
Integer: A signed binary numeric value contained
in an 8-bit byte or a 16-bit
word. All operations assume a 2's
complement representation. Signed
32 and 64-bit integers are supported
using the Numeric Data Processor,
the M80C287.
Ordinal: An unsigned binary numeric value
contained in an 8-bit byte or 16-bit
word.
Pointer: A 32-bit quantity, composed of a
segment selector component and an
offset component. Each component
is a 16-bit word.
String: A contiguous sequence of bytes or
words. A string may contain from 1
byte to 64K bytes.
ASCII: A byte representation of alphanumeric
and control characters using
the ASCII standard of character representation.
BCD: A byte (unpacked) representation of
the decimal digits 0±9.
Packed BCD: A byte (packed) representation of
two decimal digits 0±9 storing one
digit in each nibble of the byte.
Floating Point: A signed 32, 64, or 80-bit real number
representation. (Floating point
operands are supported using the
M80C287 Numeric Processor).
Figure 6 graphically represents the data types supported
by the M80C286.
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit
ports. I/O instructions address the I/O space with
either an 8-bit port address, specified in the instruction,
or a 16-bit port address in the DX register. 8-bit
port addresses are zero extended such that A15±A8
are LOW. I/O port addresses 00F8(H) through
00FF(H) are reserved.
271103±5
Figure 6. M80C286 Supported Data Types
7
M80C286
Table 4. Interrupt Vector Assignments
Interrupt Related
Does Return Address
Function
Number Instructions
Point to Instruction
Causing Exception?
Divide error exception 0 DIV, IDIV Yes
Single step interrupt 1 All
NMI interrupt 2 INT 2 or NMI pin
Breakpoint interrupt 3 INT 3
INTO detected overflow exception 4 INTO No
BOUND range exceeded exception 5 BOUND Yes
Invalid opcode exception 6 Any undefined opcode Yes
Processor extension not available exception 7 ESC or WAIT Yes
Intel reserved±do not use 8-15
Processor extension error interrupt 16 ESC or WAIT
Intel reserved±do not use 17-31
User defined 32-255
Interrupts
An interrupt transfers execution to a new program
location. The old program address (CS:IP) and machine
state (Flags) are saved on the stack to allow
resumption of the interrupted program. Interrupts fall
into three classes: hardware initiated, INT instructions,
and instruction exceptions. Hardware initiated
interrupts occur in response to an external input and
are classified as non-maskable or maskable. Programs
may cause an interrupt with an INT instruction.
Instruction exceptions occur when an unusual
condition, which prevents further instruction processing,
is detected while attempting to execute an
instruction. The return address from an exception
will always point at the instruction causing the exception
and include any leading instruction prefixes.
A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt. Interrupts
0±31, some of which are used for instruction
exceptions, are reserved. For each interrupt, an
8-bit vector must be supplied to the M80C286 which
identifies the appropriate table entry. Exceptions
supply the interrupt vector internally. INT instructions
contain or imply the vector and allow access to all
256 interrupts. The Interrupt Vector Assignments are
listed in Table 4. Maskable hardware initiated interrupts
supply the 8-bit vector to the CPU during an
interrupt acknowledge bus sequence. Non-maskable
hardware interrupts use a predefined internally
supplied vector.
MASKABLE INTERRUPT (INTR)
The M80C286 provides a maskable hardware interrupt
request pin, INTR. Software enables this input
by setting the interrupt flag bit (IF) in the flag word.
All 224 user-defined interrupt sources can share this
input, yet they can retain separate interrupt handlers.
An 8-bit vector read by the CPU during the
interrupt acknowledge sequence (discussed in System
Interface section) identifies the source of the
interrupt.
Further maskable interrupts are disabled while servicing
an interrupt by resetting the IF but as part of
the response to an interrupt or exception. The saved
flag word will reflect the enable status of the processor
prior to the interrupt. Until the flag word is restored
to the flag register, the interrupt flag will be
zero unless specifically set. The interrupt return instruction
includes restoring the flag word, thereby
restoring the original status of IF.
NON-MASKABLE INTERRUPT REQUEST (NMI)
A non-maskable interrupt input (NMI) is also provided.
NMI has higher priority than INTR. A typical use
of NMI would be to activate a power failure routine.
The activation of this input causes an interrupt with
an internally supplied vector value of 2. No external
interrupt acknowledge sequence is performed.
While executing the NMI servicing procedure, the
M80C286 will service neither further NMI requests,
INTR requests, nor the processor extension segment
overrun interrupt until an interrupt return (IRET)
instruction is executed or the CPU is reset. If NMI
occurs while currently servicing an NMI, its presence
will be saved for servicing after executing the first
IRET instruction. IF is cleared at the beginning of an
NMI interrupt to inhibit INTR interrupts.
8
M80C286
SINGLE STEP INTERRUPT
The M80C286 has an internal interrupt that allows
programs to execute one instruction at a time. It is
called the single step interrupt and is controlled by
the single step flag bit (TF) in the flag word. Once
this bit is set, an internal single step interrupt will
occur after the next instruction has been executed.
The interrupt clears the TF bit and uses an internally
supplied vector of 1. The IRET instruction is used to
set the TF bit and transfer control to the next instruction
to be single stepped.
Interrupt Priorities
When simultaneous interrupt requests occur, they
are processed in a fixed order as shown in Table 5.
Interrupt processing involves saving the flags, return
address, and setting CS:IP to point at the first instruction
of the interrupt handler. If other interrupts
remain enabled they are processed before the first
instruction of the current interrupt handler is executed.
The last interrupt processed is therefore the first
one serviced.
Table 5. Interrupt Processing Order
Order Interrupt
1 Instruction exception
2 Single step
3 NMI
4 Processor extension segment overrun
5 INTR
6 INT instruction
Initialization and Processor Reset
Processor initialization or start up is accomplished
by driving the RESET input pin HIGH. RESET forces
the M80C286 to terminate all execution and local
bus activity. No instruction or bus activity will occur
as long as RESET is active. After RESET becomes
inactive and an internal processing interval elapses,
the M80C286 begins execution in real address
mode with the instruction at physical location
FFFFF0(H). RESET also sets some registers to predefined
values as shown in Table 6.
Table6.M80C286InitialRegisterStateafterRESET
Flag word 0002(H)
Machine Status Word FFF0(H)
Instruction pointer FFF0(H)
Code segment F000(H)
Data segment 0000(H)
Extra segment 0000(H)
Stack segment 0000(H)
HOLD must not be active during the time from the
leading edge of RESET to 34 CLKs after the trailing
edge of RESET.
Machine Status Word Description
The machine status word (MSW) records when a
task switch takes place and controls the operating
mode of the M80C286. It is a 16-bit register of which
the lower four bits are used. One bit places the CPU
into protected mode, while the other three bits, as
shown in Table 7, control the processor extension
interface. After RESET, this register contains
FFF0(H) which places the M80C286 in M8086 real
address mode.
Table 7. MSW Bit Functions
Bit
Name Function
Position
0 PE Protected mode enable places the
M80C286 into protected mode and
cannot be cleared except by RESET.
1 MP Monitor processor extension allows
WAIT instructions to cause a processor
extension not present exception
(number 7).
2 EM Emulate processor extension causes a
processor extension not present
exception (number 7) on ESC
instructions to allow emulating a
processor extension.
3 TS Task switched indicates the next
instruction using a processor extension
will cause exception 7, allowing software
to test whether the current processor
extension context belongs to the current
task.
The LMSW and SMSW instructions can load and
store the MSW in real address mode. The recommended
use of TS, EM, and MP is shown in Table 8.
Table 8. Recommended MSW Encodings For Processor Extension Control
Instructions
TS MP EM Recommended Use Causing
Exception 7
0 0 0 Initial encoding after RESET. M80C286 operation is identical to M8086, 88. None
0 0 1 No processor extension is available. Software will emulate its function. ESC
1 0 1 No processor extension is available. Software will emulate its function. The current ESC
processor extension context may belong to another task.
0 1 0 A processor extension exists. None
1 1 0 A processor extension exists. The current processor extension context may belong to ESC or
another task. The Exception 7 on WAIT allows software to test for an error pending WAIT
from a previous processor extension operation.
9
M80C286
Halt
The HLT instruction stops program execution and
prevents the CPU from using the local bus until restarted.
Either NMI, INTR with IF e 1, or RESET will
force the M80C286 out of halt. If interrupted, the
saved CS:IP will point to the next instruction after
the HLT.
M8086 REAL ADDRESS MODE
The M80C286 executes a fully upward-compatible
superset of the M8086 instruction set in real address
mode. In real address mode the M80C286 is object
code compatible with M8086 and M8088 software.
The real address mode architecture (registers and
addressing modes) is exactly as described in the
M80C286 Base Architecture section of this Functional
Description.
Memory Size
Physical memory is a contiguous array of up to
1,048,576 bytes (one megabyte) addressed by pins
A0 through A19 and BHE. A20 through A23 should be
ignored.
Memory Addressing
In real address mode physical memory is a contiguous
array of up to 1,048,576 bytes (one megabyte)
addressed by pins A0 through A19 and BHE. Address
bits A20±A23 may not always be zero in real
mode. A20±A23 should not be used by the system
while the M80C286 is operating in Real Mode.
The selector portion of a pointer is interpreted as the
upper 16 bits of a 20-bit segment address. The lower
four bits of the 20-bit segment address are always
zero. Segment addresses, therefore, begin on multiples
of 16 bytes. See Figure 7 for a graphic representation
of address information.
All segments in real address mode are 64K bytes in
size and may be read, written, or executed. An exception
or interrupt can occur if data operands or
instructions attempt to wrap around the end of a
segment (e.g. a word with its low order byte at offset
FFFF(H) and its high order byte at offset 0000(H). If,
in real address mode, the information contained in a
segment does not use the full 64K bytes, the unused
end of the segment may be overlayed by another
segment to reduce physical memory requirements.
Reserved Memory Locations
The M80C286 reserves two fixed areas of memory
in real address mode (see Figure 8); system initialization
area and interrupt table area. Locations from
addresses FFFF0(H) through FFFFF(H) are reserved
for system initialization. Initial execution begins
at location FFFF0(H). Locations 00000(H)
through 003FF(H) are reserved for interrupt vectors.
271103±6
Figure 7. M8086 Real Address Mode
Address Calculation
271103±7
Figure 8. M8086 Real Address Mode Initially
Reserved Memory Locations
10
M80C286
Table 9. Real Address Mode Addressing Interrupts
Function
Interrupt Related Return Address
Number Instructions Before Instruction?
Interrupt table limit too small exception 8 INT vector is not within table limit Yes
Processor extension segment overrun 9 ESC with memory operand extend- No
interrupt ing beyond offset FFFF(H)
Segment overrun exception 13 Word memory reference with offset Yes
e FFFF(H) or an attempt to execute
past the end of a segment
Interrupts
Table 9 shows the interrupt vectors reserved for exceptions
and interrupts which indicate an addressing
error. The exceptions leave the CPU in the state existing
before attempting to execute the failing instruction
(except for PUSH, POP, PUSHA, or POPA).
Refer to the next section on protected mode initialization
for a discussion on exception 8.
Protected Mode Initialization
To prepare the M80C286 for protected mode, the
LIDT instruction is used to load the 24-bit interrupt
table base and 16-bit limit for the protected mode
interrupt table. This instruction can also set a base
and limit for the interrupt vector table in real address
mode. After reset, the interrupt table base is initialized
to 000000(H) and its size set to 03FF(H). These
values are compatible with M8086, 88 software.
LIDT should only be executed in preparation for protected
mode.
Shutdown
Shutdown occurs when a severe error is detected
that prevents further instruction processing by the
CPU. Shutdown and halt are externally signalled via
a halt bus operation. They can be distinguished by
A1 HIGH for halt and A1 LOW for shutdown. In real
address mode, shutdown can occur under two conditions:
# Exceptions 8 or 13 happen and the IDT limit does
not include the interrupt vector.
# A CALL INT or PUSH instruction attempts to wrap
around the stack segment when SP is not even.
An NMI input can bring the CPU out of shutdown if
the IDT limit is at least 000F(H) and SP is greater
than 0005(H), otherwise shutdown can only be exited
via the RESET input.
PROTECTED VIRTUAL ADDRESS
MODE
The M80C286 executes a fully upward-compatible
superset of the M8086 instruction set in protected
virtual address mode (protected mode). Protected
mode also provides memory management and protection
mechanisms and associated instructions.
The M80C286 enters protected virtual address
mode from real address mode by setting the PE
(Protection Enable) bit of the machine status word
with the Load Machine Status Word (LMSW) instruction.
Protected mode offers extended physical and
virtual memory address space, memory protection
mechanisms, and new operations to support operating
systems and virtual memory.
All registers, instructions, and addressing modes described
in the M80C286 Base Architecture section
of this Functional Description remain the same. Programs
for the M8086, 88, 186, and real address
mode M80C286 can be run in protected mode; however,
embedded constants for segment selectors
are different.
Memory Size
The protected mode M80C286 provides a 1 gigabyte
virtual address space per task mapped into a 16
megabyte physical address space defined by the address
pin A23±A0 and BHE. The virtual address
space may be larger than the physical address
space since any use of an address that does not
map to a physical memory location will cause a restartable
exception.
Memory Addressing
As in real address mode, protected mode uses 32-
bit pointers, consisting of 16-bit selector and offset
components. The selector, however, specifies an index
into a memory resident table rather than the upper
16-bits of a real memory address. The 24-bit
base address of the desired segment is obtained
11
M80C286
from the tables in memory. The 16-bit offset is added
to the segment base address to form the physical
address as shown in Figure 10. The tables are automatically
referenced by the CPU whenever a segment
register is loaded with a selector. All M80C286
instructions which load a segment register will reference
the memory based tables without additional
software. The memory based tables contain 8 byte
values called descriptors.
271103±8
Figure 9. Protected Mode Memory Addressing
DESCRIPTORS
Descriptors define the use of memory. Special types
of descriptors also define new functions for transfer
of control and task switching. The M80C286 has
segment descriptors for code, stack and data segments,
and system control descriptors for special
system data segments and control transfer operations,
see Figure 10. Descriptor accesses are performed
as locked bus operations to assure descriptor
integrity in multi-processor systems.
CODE AND DATA SEGMENT DESCRIPTORS
(S e 1)
Besides segment base addresses, code and data
descriptors contain other segment attributes including
segment size (1 to 64K bytes), access rights
(read only, read/write, execute only, and execute/
read), and presence in memory (for virtual memory
systems) (See Figure 11). Any segment usage violating
a segment attribute indicated by the segment
descriptor will prevent the memory cycle and cause
an exception or interrupt.
271103±9
*Must be set to 0 for compatibility with 80386.
Figure 10. Code or Data Segment Descriptor
Access Rights Byte Definition
Bit
Name Function
Position
7 Present (P) P e 1 Segment is mapped into physical memory.
P e 0 No mapping to physical memory exits, base and limit are
not used.
6±5 Descriptor Privilege Segment privilege attribute used in privilege tests.
Level (DPL)
4 Segment Descrip- S e 1 Code or Data (includes stacks) segment descriptor
tor (S) S e 0 System Segment Descriptor or Gate Descriptor
3 Executable (E) E e 0 Data segment descriptor type is: If
2 Expansion Direc- ED e 0 Expand up segment, offsets must be s limit. Data
tion (ED) ED e 1 Expand down segment, offsets must be l limit. Segment
1 Writeable (W) W e 0 Data segment may not be written into. (S e 1,
Type
W e 1 Data segment may be written into. * E e 0)
Field
3 Executable (E) E e 1 Code Segment Descriptor type is: If
Definition
2 Conforming (C) C e 1 Code segment may only be executed Code
when CPL tDPL and CPL Segment
remains unchanged.
1 Readable (R) R e0 Code segment may not be read (S e 1,
R e 1 Code segment may be read. * E e 1)
0 Accessed (A) A e 0 Segment has not been accessed.
A e 1 Segment selector has been loaded into segment register
or used by selector test instructions.
Figure 11. Code and Data Segment Descriptor Formats
12
M80C286
Code and data (including stack data) are stored in
two types of segments: code segments and data
segments. Both types are identified and defined by
segment descriptors (S e 1). Code segments are
identified by the executable (E) bit set to 1 in the
descriptor access rights byte. The access rights byte
of both code and data segment descriptor types
have three fields in common: present (P) bit, Descriptor
Privilege Level (DPL), and accessed (A) bit.
If P e 0, any attempted use of this segment will
cause a not-present exception. DPL specifies the
privilege level of the segment descriptor. DPL controls
when the descriptor may be used by a task
(refer to privilege discussion below). The A bit shows
whether the segment has been previously accessed
for usage profiling, a necessity for virtual memory
systems. The CPU will always set this bit when accessing
the descriptor.
Data segments (S e 1, E e 0) may be either readonly
or read-write as controlled by the W bit of the
access rights byte. Read-only (W e 0) data segments
may not be written into. Data segments may
grow in two directions, as determined by the Expansion
Direction (ED) bit: upwards (ED e 0) for data
segments, and downwards (ED e 1) for a segment
containing a stack. The limit field for a data segment
descriptor is interpreted differently depending on the
ED bit (see Figure 11).
A code segment (S e 1, E e 1) may be executeonly
or execute/read as determined by the Readable
(R) bit. Code segments may never be written
into and execute-only code segments (R e 0) may
not be read. A code segment may also have an attribute
called conforming (C). A conforming code segment
may be shared by programs that execute at
different privilege levels. The DPL of a conforming
code segment defines the range of privilege levels
at which the segment may be executed (refer to privilege
discussion below). The limit field identifies the
last byte of a code segment.
SYSTEM SEGMENT DESCRIPTORS (S e 0,
TYPE e 1±3)
In addition to code and data segment descriptors,
the protected mode M80C286 defines System Segment
Descriptors. These descriptors define special
system data segments which contain a table of descriptors
(Local Descriptor Table Descriptor) or segments
which contain the execution state of a task
(Task State Segment Descriptor).
Figure 12 gives the formats for the special system
data segment descriptors. The descriptors contain a
24-bit base address of the segment and a 16-bit limit.
The access byte defines the type of descriptor, its
state and privilege level. The descriptor contents are
valid and the segment is in physical memory if P e1.
If P e 0, the segment is not valid. The DPL field is
only used in Task State Segment descriptors and
indicates the privilege level at which the descriptor
may be used (see Privilege). Since the Local Descriptor
Table descriptor may only be used by a special
privileged instruction, the DPL field is not used.
Bit 4 of the access byte is 0 to indicate that it is a
system control descriptor. The type field specifies
the descriptor type as indicated in Figure 12.
System Segment Descriptor
271103±10
*Must be set to 0 for compatibility with 80386.
System Segment Descriptor Fields
Name Value Description
TYPE 1 Available Task State Segment (TSS)
2 Local Descriptor Table
3 Busy Task State Segment (TSS)
P 0 Descriptor contents are not valid
1 Descriptor contents are valid
DPL 0±3 Descriptor Privilege Level
BASE 24-bit Base Address of special system data
number segment in real memory
LIMIT 16-bit Offset of last byte in segment
number
Figure 12. System Segment Descriptor Format
GATE DESCRIPTORS (S e 0, TYPE e 4±7)
Gates are used to control access to entry points
within the target code segment. The gate descriptors
are call gates, task gates, interrupt gates and
trap gates. Gates provide a level of indirection between
the source and destination of the control
transfer. This indirection allows the CPU to automatically
perform protection checks and control entry
point of the destination. Call gates are used to
change privilege levels (see Privilege), task gates
are used to perform a task switch, and interrupt and
trap gates are used to specify interrupt service routines.
The interrupt gate disables interrupts (resets
IF) while the trap gate does not.
Figure 13 shows the format of the gate descriptors.
The descriptor contains a destination pointer that
points to the descriptor of the target segment and
the entry point offset. The destination selector in an
interrupt gate, trap gate, and call gate must refer to a
code segment descriptor. These gate descriptors
contain the entry point to prevent a program from
constructing and using an illegal entry point. Task
gates may only refer to a task state segment. Since
task gates invoke a task switch, the destination offset
is not used in the task gate.
13
M80C286
Gate Descriptor
271103±11
*Must be set to 0 for compatibility with 80386 (X is don't care)
Gate Descriptor Fields
Name Value Description
4 ±Call Gate
TYPE
5 ±Task Gate
6 ±Interrupt Gate
7 ±Trap Gate
P 0 ±Descriptor Contents are not
valid
1 ±Descriptor Contents are
valid
DPL 0±3 Descriptor Privilege Level
WORD Number of words to copy
COUNT
0±31
from callers stack to called
procedures stack. Only used
with call gate.
Selector to the target code
DESTINATION 16-bit
segment (Call, Interrupt or
SELECTOR selector
Trap Gate)
Selector to the target task
state segment (Task Gate)
DESTINATION 16-bit Entry point within the target
OFFSET offset code segment
Figure 13. Gate Descriptor Format
Exception 13 is generated when the gate is used if a
destination selector does not refer to the correct descriptor
type. The word count field is used in the call
gate descriptor to indicate the number of parameters
(0±31 words) to be automatically copied from the
caller's stack to the stack of the called routine when
a control transfer changes privilege levels. The word
count field is not used by any other gate descriptor.
The access byte format is the same for all gate descriptors.
P e 1 indicates that the gate contents are
valid. P e 0 indicates the contents are not valid and
causes exception 11 if referenced. DPL is the descriptor
privilege level and specifies when this descriptor
may be used by a task (refer to privilege
discussion below). Bit 4 must equal 0 to indicate a
system control descriptor. The TYPE field specifies
the descriptor type as indicated in Figure 13.
SEGMENT DESCRIPTOR CACHE REGISTERS
A segment descriptor cache register is assigned to
each of the four segment registers (CS, SS, DS, ES).
Segment descriptors are automatically loaded
(cached) into a segment descriptor cache register
(Figure 14) whenever the associated segment register
is loaded with a selector. Only segment descriptors
may be loaded into segment descriptor cache
registers. Once loaded, all references to that segment
of memory use the cached descriptor information
instead of reaccessing the descriptor. The descriptor
cache registers are not visible to programs.
No instructions exist to store their contents. They
only change when a segment register is loaded.
SELECTOR FIELDS
A protected mode selector has three fields: descriptor
entry index, local or global descriptor table indicator
(TI), and selector privilege (RPL) as shown in
Figure 15. These fields select one of two memory
based tables of descriptors, select the appropriate
table entry and allow highspeed testing of the selector's
privilege attribute (refer to privilege discussion
below).
271103±12
Figure 15. Selector Fields
271103±13
Figure 14. Descriptor Cache Registers
14
M80C286
LOCAL AND GLOBAL DESCRIPTOR TABLES
Two tables of descriptors, called descriptor tables,
contain all descriptors accessible by a task at any
given time. A descriptor table is a linear array of up
to 8192 descriptors. The upper 13 bits of the selector
value are an index into a descriptor table. Each
table has a 24-bit base register to locate the descriptor
table in physical memory and a 16-bit limit register
that confine descriptor access to the defined limits
of the table as shown in Figure 16. A restartable
exception (13) will occur if an attempt is made to
reference a descriptor outside the table limits.
One table, called the Global Descriptor table (GDT),
contains descriptors available to all tasks. The other
table, called the Local Descriptor Table (LDT), contains
descriptors that can be private to a task. Each
task may have its own private LDT. The GDT may
contain all descriptor types except interrupt and trap
descriptors. The LDT may contain only segment,
task gate, and call gate descriptors. A segment cannot
be accessed by a task if its segment descriptor
does not exist in either descriptor table at the time of
access.
271103±14
Figure 16. Local and Global
Descriptor Table Definition
The LGDT and LLDT instructions load the base and
limit of the global and local descriptor tables. LGDT
and LLDT are privileged, i.e. they may only be executed
by trusted programs operating at level 0. The
LGDT instruction loads a six byte field containing the
16-bit table limit and 24-bit physical base address of
the Global Descriptor Table as shown in Figure 17.
The LDT instruction loads a selector which refers to
a Local Descriptor Table descriptor containing the
base address and limit for an LDT, as shown in Figure
16.
271103±15
*Must be set to 0 for compatibility with 80386.
Figure 17. Global Descriptor Table and
Interrupt Descriptor Table Data Type
INTERRUPT DESCRIPTOR TABLE
The protected mode M80C286 has a third descriptor
table, called the Interrupt Descriptor Table (IDT)
(see Figure 18), used to define up to 256 interrupts.
It may contain only task gates, interrupt gates and
trap gates. The IDT (Interrupt Descriptor Table) has
a 24-bit physical base and 16-bit limit register in the
CPU. The privileged LIDT instruction loads these
registers with a six byte value of identical form to
that of the LGDT instruction (see Figure 17 and Protected
Mode Initialization).
271103±16
Figure 18. Interrupt Descriptor Table Definition
References to IDT entries are made via INT instructions,
external interrupt vectors, or exceptions. The
IDT must be at least 256 bytes in size to allocate
space for all reserved interrupts.
Privilege
The M80C286 has a four-level hierarchical privilege
system which controls the use of privileged instructions
and access to descriptors (and their associated
segments) within a task. Four-level privilege, as
shown in Figure 19, is an extension of the user/supervisor
mode commonly found in minicomputers.
The privilege levels are numbered 0 through 3.
15
M80C286
271103±17
Figure 19. Privilege Levels
Level 0 is the most privileged level. Privilege levels
provide protection within a task. (Tasks are isolated
by providing private LDT's for each task.) Operating
system routines, interrupt handlers, and other system
software can be included and protected within
the virtual address space of each task using the four
levels of privilege. Each task in the system has a
separate stack for each of its privilege levels.
Tasks, descriptors, and selectors have a privilege
level attribute that determines whether the descriptor
may be used. Task privilege effects the use of
instructions and descriptors. Descriptor and selector
privilege only effect access to the descriptor.
TASK PRIVILEGE
A task always executes at one of the four privilege
levels. The task privilege level at any specific instant
is called the Current Privilege Level (CPL) and is defined
by the lower two bits of the CS register. CPL
cannot change during execution in a single code
segment. A task's CPL may only be changed by control
transfers through gate descriptors to a new code
segment (See Control Transfer). Tasks begin executing
at the CPL value specified by the code segment
selector within TSS when the task is initiated
via a task switch operation (See Figure 20). A task
executing at Level 0 can access all data segments
defined in the GDT and the task's LDT and is considered
the most trusted level. A task executing a
Level 3 has the most restricted access to data and is
considered the least trusted level.
DESCRIPTOR PRIVILEGE
Descriptor privilege is specified by the Descriptor
Privilege Level (DPL) field of the descriptor access
byte. DPL specifies the least trusted task privilege
level (CPL) at which a task may access the descriptor.
Descriptors with DPL e 0 are the most protected.
Only tasks executing at privilege level 0
(CPL e 0) may access them. Descriptors with DPL
e 3 are the least protected (i.e. have the least restricted
access) since tasks can access them when
CPL e 0, 1, 2, or 3. This rule applies to all descriptors,
except LDT descriptors.
SELECTOR PRIVILEGE
Selector privilege is specified by the Requested Privilege
Level (RPL) field in the least significant two bits
of a selector. Selector RPL may establish a less
trusted privilege level than the current privilege level
for the use of a selector. This level is called the
task's effective privilege level (EPL). RPL can only
reduce the scope of a task's access to data with this
selector. A task's effective privilege is the numeric
maximum of RPL and CPL. A selector with RPL e 0
imposes no additional restriction on its use while a
selector with RPL e 3 can only refer to segments at
privilege Level 3 regardless of the task's CPL. RPL
is generally used to verify that pointer parameters
passed to a more trusted procedure are not allowed
to use data at a more privileged level than the caller
(refer to pointer testing instructions).
Descriptor Access and Privilege
Validation
Determining the ability of a task to access a segment
involves the type of segment to be accessed,
the instruction used, the type of descriptor used and
CPL, RPL, and DPL. The two basic types of segment
accesses are control transfer (selectors loaded into
CS) and data (selectors loaded into DS, ES or SS).
DATA SEGMENT ACCESS
Instructions that load selectors into DS and ES must
refer to a data segment descriptor or readable code
segment descriptor. The CPL of the task and the
RPL of the selector must be the same as or more
privileged (numerically equal to or lower than) than
the descriptor DPL. In general, a task can only access
data segments at the same or less privileged
levels than the CPL or RPL (whichever is numerically
higher) to prevent a program from accessing data it
cannot be trusted to use.
An exception to the rule is a readable conforming
code segment. This type of code segment can be
read from any privilege level.
If the privilege checks fail (e.g. DPL is numerically
less than the maximum of CPL and RPL) or an incorrect
type of descriptor is referenced (e.g. gate de-
16
M80C286
scriptor or execute only code segment) exception 13
occurs. If the segment is not present, exception 11
is generated.
Instructions that load selectors into SS must refer to
data segment descriptors for writable data segments.
The descriptor privilege (DPL) and RPL must
equal CPL. All other descriptor types or a privilege
level violation will cause exception 13. A not present
fault causes exception 12.
CONTROL TRANSFER
Four types of control transfer can occur when a selector
is loaded into CS by a control transfer operation
(see Table 10). Each transfer type can only occur
if the operation which loaded the selector references
the correct descriptor type. Any violation of
these descriptor usage rules (e.g. JMP through a call
gate or RET to a Task State Segment) will cause
exception 13.
The ability to reference a descriptor for control transfer
is also subject to rules of privilege. A CALL or
JUMP instruction may only reference a code segment
descriptor with DPL equal to the task CPL or a
conforming segment with DPL of equal or greater
privilege than CPL. The RPL of the selector used to
reference the code descriptor must have as much
privilege as CPL.
RET and IRET instructions may only reference code
segment descriptors with descriptor privilege equal
to or less privileged than the task CPL. The selector
loaded into CS is the return address from the stack.
After the return, the selector RPL is the task's new
CPL. If CPL changes, the old stack pointer is popped
after the return address.
When a JMP or CALL references a Task State Segment
descriptor, the descriptor DPL must be the
same or less privileged than the task's CPL. Reference
to a valid Task State Segment descriptor causes
a task switch (see Task Switch Operation). Reference
to a Task State Segment descriptor at a more
privileged level than the task's CPL generates exception
13.
When an instruction or interrupt references a gate
descriptor, the gate DPL must have the same or less
privilege than the task CPL. If DPL is at a more privileged
level than CPL, exeception 13 occurs. If the
destination selector contained in the gate references
a code segment descriptor, the code segment
descriptor DPL must be the same or more privileged
than the task CPL. If not, Exception 13 is issued.
After the control transfer, the code segment
descriptors DPL is the task's new CPL. If the destination
selector in the gate references a task state
segment, a task switch is automatically performed
(see Task Switch Operation).
The privilege rules on control transfer require:
Ð JMP or CALL direct to a code segment (code
segment descriptor) can only be to a conforming
segment with DPL of equal or greater privilege
than CPL or a non-conforming segment at the
same privilege level.
Ð interrupts within the task or calls that may
change privilege levels, can only transfer control
through a gate at the same or a less privileged
level than CPL to a code segment at the same or
more privileged level than CPL.
Ð return instructions that don't switch tasks can
only return control to a code segment at the
same or less privileged level.
Ð task switch can be performed by a call, jump or
interrupt which references either a task gate or
task state segment at the same or less privileged
level.
Table 10. Descriptor Types Used for Control Transfer
Control Transfer Types Operation Types
Descriptor Descriptor
Referenced Table
Intersegment within the same privilege level JMP, CALL, RET, IRET* Code Segment GDT/LDT
Intersegment to the same or higher privilege level Interrupt CALL Call Gate GDT/LDT
within task may change CPL. Interrupt Instruction, Trap or IDT
Exception, External Interrupt
Interrupt Gate
Intersegment to a lower privilege level (changes task CPL) RET, IRET* Code Segment GDT/LDT
CALL, JMP Task State GDT
Segment
Task Switch
CALL, JMP Task Gate GDT/LDT
IRET**
Interrupt Instruction,
Task Gate IDT
Exception, External
Interrupt
*NT (Nested Task bit of flag word) e 0
**NT (Nested Task bit of flag word) e 1
17
M80C286
PRIVILEGE LEVEL CHANGES
Any control transfer that changes CPL within the
task, causes a change of stacks as part of the operation.
Initial values of SS:SP for privilege levels 0, 1,
and 2 are kept in the task state segment (refer to
Task Switch Operation). During a JMP or CALL control
transfer, the new stack pointer is loaded into the
SS and SP registers and the previous stack pointer
is pushed onto the new stack.
When returning to the original privilege level, its
stack is restored as part of the RET or IRET instruction
operation. For subroutine calls that pass parameters
on the stack and cross privilege levels, a fixed
number of words, as specified in the gate, are copied
from the previous stack to the current stack. The
inter-segment RET instruction with a stack adjustment
value will correctly restore the previous stack
pointer upon return.
Protection
The M80C286 includes mechanisms to protect critical
instructions that affect the CPU execution state
(e.g. HLT) and code or data segments from improper
usage. These protection mechanisms are grouped
into three forms:
Restricted usage of segments (e.g. no write allowed
to read-only data segments). The only segments
available for use are defined by descriptors
in the Local Descriptor Table (LDT) and
Global Descriptor Table (GDT).
Restricted access to segments via the rules of
privilege and descriptor usage.
Privileged instructions or operations that may
only be executed at certain privilege levels as determined
by the CPL and I/O Privilege Level
(IOPL). The IOPL is defined by bits 14 and 13 of
the flag word.
These checks are performed for all instructions and
can be split into three categories: segment load
checks (Table 11), operand reference checks (Table
12), and privileged instruction checks (Table 13).
Any violation of the rules shown will result in an exception.
A not-present exception related to the stack
segment causes exception 12.
The IRET and POPF instructions do not perform
some of their defined functions if CPL is not of sufficient
privilege (numerically small enough). Precisely
these are:
# The IF bit is not changed if CPL l IOPL.
# The IOPL field of the flag word is not changed if
CPL l 0.
No exceptions or other indication are given when
these conditions occur.
Table 11. Segment Register Load Checks
Error Description
Exception
Number
Descriptor table limit exceeded 13
Segment descriptor not-present 11 or 12
Privilege rules violated 13
Invalid descriptor/segment type segment
register load:
ÐRead only data segment load to
SS
ÐSpecial Control descriptor load to
DS, ES, SS 13
ÐExecute only segment load to
DS, ES, SS
ÐData segment load to CS
ÐRead/Execute code segment
load to SS
Table 12. Operand Reference Checks
Error Description
Exception
Number
Write into code segment 13
Read from execute-only code
segment 13
Write to read-only data segment 13
Segment limit exceeded1 12 or 13
NOTE:
Carry out in offset calculations is ignored.
Table 13. Privileged Instruction Checks
Error Description
Exception
Number
CPL i 0 when executing the following
instructions:
13
LIDT, LLDT, LGDT, LTR, LMSW,
CTS, HLT
CPL l IOPL when executing the following
instructions:
13
INS, IN, OUTS, OUT, STI, CLI,
LOCK
EXCEPTIONS
The M80C286 detects several types of exceptions
and interrupts, in protected mode (see Table 14).
Most are restartable after the exceptional condition
is removed. Interrupt handlers for most exceptions
can read an error code, pushed on the stack after
the return address, that identifies the selector involved
(0 if none). The return address normally
points to the failing instruction, including all leading
prefixes. For a processor extension segment overrun
exception, the return address will not point at the
ESC instruction that caused the exception; however,
the processor extension registers may contain the
address of the failing instruction.
18
M80C286
Table 14. Protected Mode Exceptions
Return
Always Error
Interrupt
Function
Address
Restart- Code
Vector At Falling
able? on Stack?
Instruction?
8 Double exception detected Yes No2 Yes
9 Processor extension segment overrun No No2 No
10 Invalid task state segment Yes Yes Yes
11 Segment not present Yes Yes Yes
12 Stack segment overrun or stack segment not present Yes Yes1 Yes
13 General protection Yes No2 Yes
NOTE:
1. When a PUSHA or POPA instruction attempts to wrap around the stack segment, the machine state after the exception
will not be restartable because stack segment wrap around is not permitted. This condition is identified by the value of the
saved SP being either 0000(H), 0001(H), FFFE(H), or FFFF(H).
2. These exceptions indicate a violation to privilege rules or usage rules has occurred. Restart is generally not attempted
under those conditions.
These exceptions indicate a violation to privilege
rules or usage rules has occurred. Restart is generally
not attempted under those conditions.
All these checks are performed for all instructions
and can be split into three categories: segment load
checks (Table 11), operand reference checks (Table
12), and privileged instruction checks (Table 13).
Any violation of the rules shown will result in an exception.
A not-present exception causes exception
11 or 12 and is restartable.
Special Operations
TASK SWITCH OPERATION
The M80C286 provides a built-in task switch operation
which saves the entire M80C286 execution
state (registers, address space, and a link to the previous
task), loads a new execution state, and commences
execution in the new task. Like gates, the
task switch operation is invoked by executing an inter-
segment JMP or CALL instruction which refers to
a Task State Segment (TSS) or task gate descriptor
in the GDT or LDT. An INT n instruction, exception,
or external interrupt may also invoke the task switch
operation by selecting a task gate descriptor in the
associated IDT descriptor entry.
The TSS descriptor points at a segment (see Figure
20) containing the entire M80C286 execution state
while a task gate descriptor contains a TSS selector.
The limit field of the descriptor must be l002B(H).
Each task must have a TSS associated with it. The
current TSS is identified by a special register in the
M80C286 called the Task Register (TR). This register
contains a selector referring to the task state
segment descriptor that defines the current TSS. A
hidden base and limit register associated with TR
are loaded whenever TR is loaded with a new selector.
The IRET instruction is used to return control to the
task that called the current task or was interrupted.
Bit 14 in the flag register is called the Nested Task
(NT) bit. It controls the function of the IRET instruction.
If NT e 0, the IRET instruction performs the
regular current task by popping values off the stack;
when NT e 1, IRET performs a task switch operation
back to the previous task.
When a CALL, JMP, or INT instruction initiates a
task switch, the old (except for case of JMP) and
new TSS will be marked busy and the back link field
of the new TSS set to the old TSS selector. The NT
bit of the new task is set by CALL or INT initiated
task switches. An interrupt that does not cause a
task switch will clear NT. NT may also be set or
cleared by POPF or IRET instructions.
The task state segment is marked busy by changing
the descriptor type field from Type 1 to Type 3. Use
of a selector that references a busy task state segment
causes Exception 13.
PROCESSOR EXTENSION CONTEXT
SWITCHING
The context of a processor extension (such as the
M80C287 numerics processor) is not changed by
the task switch operation. A processor extension
context need only be changed when a different task
attempts to use the processor extension (which still
contains the context of a previous task). The
M80C286 detects the first use of a processor extension
after a task switch by causing the processor
extension not present exception (7). The interrupt
handler may then decide whether a context change
is necessary.
Whenever the M80C286 switches tasks, it sets the
Task Switched (TS) bit of the MSW. TS indicates
that a processor extension context may belong to a
different task than the current one. The processor
extension not present exception (7) will occur when
attempting to execute an ESC or WAIT instruction if
TSe1 and a processor extension is present (MPe1
in MSW).
19
M80C286
POINTER TESTING INSTRUCTIONS
The M80C286 provides several instructions to
speed pointer testing and consistency checks for
maintaining system integrity (see Table 15). These
instructions use the memory management hardware
to verify that a selector value refers to an appropriate
segment without risking an exception. A condition
flag (ZF) indicates whether use of the selector
or segment will cause an exception.
271103±18
Figure 20. Task State Segment and TSS Registers
20
M80C286
Table 15. M80C286 Pointer Test Instructions
Instruction Operands Function
ARPL Selector, Adjust Requested Privilege
Register Level: adjusts the RPL of
the selector to the numeric
maximum of current selector
RPL value and the RPL
value in the register. Set
zero flag if selector RPL
was changed by ARPL.
VERR Selector VERify for Read: sets the
zero flag if the segment referred
to by the selector
can be read.
VERW Selector VERify for Write: sets the
zero flag if the segment referred
to by the selector
can be written.
LSL Register, Load Segment Limit: reads
Selector the segment limit into the
register if privilege rules
and descriptor type allow.
Set zero flag if successful.
LAR Register, Load Access Rights: reads
Selector the descriptor access
rights byte into the register
if privilege rules allow. Set
zero flag if successful.
DOUBLE FAULT AND SHUTDOWN
If two separate exceptions are detected during a single
instruction execution, the M80C286 performs the
double fault exception (8). If an execution occurs
during processing of the double fault exception, the
M80C286 will enter shutdown. During shutdown no
further instructions or exceptions are processed. Either
NMI (CPU remains in protected mode) or RESET
(CPU exits protected mode) can force the
M80C286 out of shutdown. Shutdown is externally
signalled via a HALT bus operation with A1 LOW.
PROTECTED MODE INITIALIZATION
The M80C286 initially executes in real address
mode after RESET. To allow initialization code to be
placed at the top of physical memory, A23±A20 will
be HIGH when the M80C286 performs memory references
relative to the CS register until CS is
changed. A23±A20 will be zero for references to the
DS, ES, or SS segments. Changing CS in real address
mode will force A23±A20 LOW whenever CS is
used again. The initial CS:IP value of F000:FFF0
provides 64K bytes of code space for initialization
code without changing CS.
Protected mode operation requires several registers
to be initialized. The GDT and IDT base registers
must refer to a valid GDT and IDT. After executing
the LMSW instruction to set PE, the M80C286 must
immediately execute an intra-segment JMP instruction
to clear the instruction queue of instructions decoded
in real address mode.
To force the M80C286 CPU registers to match the
initial protected mode state assumed by software,
execute a JMP instruction with a selector referring to
the initial TSS used in the system. This will load the
task register, local descriptor table register, segment
registers and initial general register state. The TR
should point at a valid TSS since any task switch
operation involves saving the current task state.
SYSTEM INTERFACE
The M80C286 system interface appears in two
forms: a local bus and a system bus. The local bus
consists of address, data, status, and control signals
at the pins of the CPU. A system bus is any buffered
version of the local bus. A system bus may also differ
from the local bus in terms of coding of status
and control lines and/or timing and loading of signals.
The M80C286 family includes several devices
to generate standard system buses such as the
IEEE 796 standard MULTIBUS.
Bus Interface Signals and Timing
The M80C286 microsystem local bus interfaces the
M80C286 to local memory and I/O components.
The interface has 24 address lines, 16 data lines,
and 8 status and control signals.
The M80C286 CPU, M82C284 clock generator,
M82C288 bus controller, transceivers, and latches
provide a buffered and decoded system bus interface.
The M82C284 generates the system clock and
synchronizes READY and RESET. The M82C288
converts bus operation status encoded by the
M80C286 into command and bus control signals.
These components can provide the timing and electrical
power drive levels required for most system
bus interfaces including the Multibus.
Physical Memory and I/O Interface
A maximum of 16 megabytes of physical memory
can be addressed in protected mode. One megabyte
can be addressed in real address mode. Memory
is accessible as bytes or words. Words consist of
any two consecutive bytes addressed with the least
significant byte stored in the lowest address.
Byte transfers occur on either half of the 16-bit local
data bus. Even bytes are accessed over D7±D0
while odd bytes are transferred over D15±D8. Evenaddressed
words are transferred over D15±D0 in
one bus cycle, while odd-addressed word require
two bus operations. The first transfers data on
D15±D8, and the second transfers data on D7±D0.
Both byte data transfers occur automatically, transparent
to software.
21
M80C286
Two bus signals, A0 and BHE, control transfers over
the lower and upper halves of the data bus. Even
address byte transfers are indicated by A0 LOW and
BHE HIGH. Odd address byte transfers are indicated
by A0 HIGH and BHE LOW. Both A0 and BHE are
LOW for even address word transfers.
The I/O address space contains 64K addresses in
both modes. The I/O space is accessible as either
bytes or words, as is memory. Byte wide peripheral
devices may be attached to either the upper or lower
byte of the data bus. Byte-wide I/O devices attached
to the upper data byte (D15±D8) are accessed with
odd I/O addresses. Devices on the lower data byte
are accessed with even I/O addresses. An interrupt
controller such as Intel's 82C59A-2 must be connected
to the lower data byte (D7±D0) for proper
return of the interrupt vector.
Bus Operation
The M80C286 uses a double frequency system
clock (CLK input) to control bus timing. All signals on
the local bus are measured relative to the system
CLK input. The CPU divides the system clock by 2 to
produce the internal processor clock, which determines
bus state. Each processor clock is composed
of two system clock cycles named phase 1 and
phase 2. The M82C284 clock generator output
(PCLK) identifies the next phase of the processor
clock. (See Figure 21.)
271103±19
Figure 21. System and Processor
Clock Relationships
Six types of bus operations are supported; memory
read, memory write, I/O read, I/O write, interrupt acknowledge,
and halt/shutdown. Data can be transferred
at a maximum rate of one word per two processor
clock cycles.
The M80C286 bus has three basic states: idle (Ti),
send status (Ts), and perform command (Tc). The
M80C286 CPU also has a fourth local bus state
called hold (Th). Th indicates that the M80C286 has
surrendered control of the local bus to another bus
master in response to a HOLD request.
Each bus state is one processor clock long. Figure
22 shows the four M80C286 local bus states and
allowed transitions.
271103±20
Figure 22. M80C286 Bus States
Bus States
The idle (Ti) state indicates that no data transfers
are in progress or requested. The first active state
TS is signaled by status line S1 or S0 going LOW
and identifying phase 1 of the processor clock. During
TS, the command encoding, the address, and
data (for a write operation) are available on the
M80C286 output pins. The M82C288 bus controller
decodes the status signals and generates Multibus
compatible read/write command and local transceiver
control signals.
After TS, the perform command (TC) state is entered.
Memory or I/O devices respond to the bus
operation during TC, either transferring read data to
the CPU or accepting write data. TC states may be
repeated as often as necessary to assure sufficient
time for the memory or I/O device to respond. The
READY signal determines whether TC is repeated. A
repeated TC state is called a wait state.
During hold (Th), the M80C286 will float* all address,
data, and status output pins enabling another bus
master to use the local bus. The M80C286 HOLD
input signal is used to place the M80C286 into the
Th state. The M80C286 HLDA output signal indicates
that the CPU has entered Th.
Pipelined Addressing
The M80C286 uses a local bus interface with pipelined
timing to allow as much time as possible for
data access. Pipelined timing allows a new bus operation
to be initiated every two processor cycles,
while allowing each individual bus operation to last
for three processor cycles.
The timing of the address outputs is pipelined such
that the address of the next bus operation becomes
available during the current bus operation. Or in other
words, the first clock of the next bus operation is
overlapped with the last clock of the current bus operation.
Therefore, address decode and routing logic
can operate in advance of the next bus operation.
*NOTE:
See section on bus hold circuitry.
22
M80C286
271103±21
Figure 23. Basic Bus Cycle
External address latches may hold the address stable
for the entire bus operation, and provide additional
AC and DC buffering.
The M80C286 does not maintain the address of the
current bus operation during all Tc states. Instead,
the address for the next bus operation may be emitted
during phase 2 of any Tc. The address remains
valid during phase 1 of the first Tc to guarantee hold
time, relative to ALE, for the address latch inputs.
Bus Control Signals
The M82C288 bus controller provides control signals;
address latch enable (ALE), Read/Write commands,
data transmit/receive (DT/R), and data enable
(DEN) that control the address latches, data
transceivers, write enable, and output enable for
memory and I/O systems.
The Address Latch Enable (ALE) output determines
when the address may be latched. ALE provides at
least one system CLK period of address hold time
from the end of the previous bus operation until the
address for the next bus operation appears at the
latch outputs. This address hold time is required to
support MULTIBUS and common memory systems.
The data bus transceivers are controlled by
M82C288 outputs Data Enable (DEN) and Data
Transmit/Receive (DT/R). DEN enables the data
transceivers; while DT/R controls tranceiver direction.
DEN and DT/R are timed to prevent bus contention
between the bus master, data bus transceivers,
and system data bus transceivers.
Command Timing Controls
Two system timing customization options, command
extension and command delay, are provided on the
M80C286 local bus.
Command extension allows additional time for external
devices to respond to a command and is analogous
to inserting wait states on the M8086. External
logic can control the duration of any bus operation
such that the operation is only as long as necessary.
The READY input signal can extend any bus operation
for as long as necessary, see Figure 23.
Command delay allows an increase of address or
write data setup time to system bus command active
for any bus operation by delaying when the system
bus command becomes active. Command delay is
controlled by the M82C288 CMDLY input. After TS,
the bus controller samples CMDLY at each failing
edge of CLK. If CMDLY is HIGH, the M82C288 will
not activate the command signal. When CMDLY is
LOW, the M82C288 will activate the command signal.
After the command becomes active, the CMDLY
input is not sampled.
When a command is delayed, the available response
time from command active to return read
data or accept write data is less. To customize system
bus timing, an address decoder can determine
which bus operations require delaying the command.
The CMDLY input does not affect the timing
of ALE, DEN, or DT/R.
23
M80C286
271103±22
Figure 24. CMDLY Controls the Leading Edge of Command Signal
Figure 24 illustrates four uses of CMDLY. Example 1
shows delaying the read command two system
CLKs for cycle N-1 and no delay for cycle N, and
example 2 shows delaying the read command one
system CLK for cycle N-1 and one system CLK delay
for cycle N.
Bus Cycle Termination
At maximum transfer rates, the M80C286 bus alternates
between the status and command states. The
bus status signals become inactive after Ts so that
they may correctly signal the start of the next bus
operation after the completion of the current cycle.
No external indication of Tc exists on the M80C286
local bus. The bus master and bus controller enter
Tc directly after Ts and continue executing Tc cycles
until terminated by READY.
READY Operation
The current bus master and M82C288 bus controller
terminate each bus operation simultaneously to
achieve maximum bus operation bandwidth. Both
are informed in advance by READY active (opencollector
output from M82C284) which identifies the
last TC cycle of the current bus operation. The bus
master and bus controller must see the same sense
of the READY signal, thereby requiring READY be
synchronous to the system clock.
Synchronous Ready
The M82C284 clock generator provides READY
synchronization from both synchronous and asynchronous
sources (see Figure 25). The synchronous
ready input (SRDY) of the clock generator is sampled
with the falling edge of CLK at the end of phase
1 of each Tc. The state of SRDY is then broadcast to
the bus master and bus controller via the READY
output line.
Asynchronous Ready
Many systems have devices or subsystems that are
asynchronous to the system clock. As a result, their
ready outputs cannot be guaranteed to meet the
M82C284 SRDY setup and hold time requirements.
But the M82C284 asynchronous ready input (ARDY)
is designed to accept such signals. The ARDY input
is sampled at the beginning of each TC cycle by
M82C284 synchronization logic. This provides one
system CLK cycle time to resolve its value before
broadcasting it to the bus master and bus controller.
24
M80C286
NOTES: 271103±23
1. SRDYEN is active low.
2. If SRDYEN is high, the state of SRDY will no affect READY.
3. ARDYEN is active low.
Figure 25. Synchronous and Asynchronous Ready
ARDY or ARDYEN must be HIGH at the end of TS.
ARDY cannot be used to terminate bus cycle with no
wait states.
Each ready input of the M82C284 has an enable pin
(SRDYEN and ARDYEN) to select whether the current
bus operation will be terminated by the synchronous
or asynchronous ready. Either of the ready inputs
may terminate a bus operation. These enable
inputs are active low and have the same timing as
their respective ready inputs. Address decode logic
usually selects whether the current bus operation
should be terminated by ARDY or SRDY.
Data Bus Control
Figures 26, 27, and 28 show how the DT/R, DEN,
data bus, and address signals operate for different
combinations of read, write, and idle bus operations.
DT/R goes active (LOW) for a read operation. DT/R
remains HIGH before, during, and between write operations.
The data bus is driven with write data during the
second phase of Ts. The delay in write data timing
allows the read data drivers, from a previous read
cycle, sufficient time to enter 3-state OFF* before
the M80C286 CPU begins driving the local data bus
for write operations. Write data will always remain
valid for one system clock past the last Tc to provide
sufficient hold time for Multibus or other similar
memory or I/O systems. During write-read or writeidle
sequences the data bus enters 3-state OFF*
during the second phase of the processor cycle after
the last Tc. In a write-write sequence the data bus
does not enter 3-state OFF* between Tc and Ts.
Bus Usage
The M80C286 local bus may be used for several
functions: instruction data transfers, data transfers
by other bus masters, instruction fetching, processor
extension data transfers, interrupt acknowledge, and
halt/shutdown. This section describes local bus activities
which have special signals or requirements.
*NOTE:
See section on bus hold circuitry.
25
M80C286
271103±24
Figure 26. Back to Back Read-Write Cycles
271103±25
Figure 27. Back to Back Write-Read Cycles
26
M80C286
271103±26
Figure 28. Back to Back Write-Write Cycles
HOLD and HLDA
HOLD AND HLDA allow another bus master to gain
control of the local bus by placing the M80C286 bus
into the Th state. The sequence of events required
to pass control between the M80C286 and another
local bus master are shown in Figure 29.
In this example, the M80C286 is initially in the Th
state as signaled by HLDA being active. Upon leaving
Th, as signaled by HLDA going inactive, a write
operation is started. During the write operation another
local bus master requests the local bus from
the M80C286 as shown by the HOLD signal. After
completing the write operation, the M80C286 performs
one Ti bus cycle, to guarantee write data hold
time, then enters Th as signaled by HLDA going active.
The CMDLY signal and ARDY ready are used to
start and stop the write bus command, respectively.
Note that SRDY must be inactive or disabled by
SRDYEN to guarantee ARDY will terminate the cycle.
HOLD must not be active during the time from the
leading edge of RESET until 34 CLKs following the
trailing edge of RESET.
Lock
The CPU asserts an active lock signal during Interrupt-
Acknowledge cycles, the XCHG instruction, and
during some descriptor accesses. Lock is also asserted
when the LOCK prefix is used. The LOCK
prefix may be used with the following ASM-286 assembly
instructions; MOVS, INS, and OUTS. For bus
cycles other than Interrupt-Acknowledge cycles,
Lock will be active for the first and subsequent cycles
of a series of cycles to be locked. Lock will not
be shown active during the last cycle to be locked.
For the next-to-last cycle, Lock will become inactive
at the end of the first Tc regardless of the number of
wait-states inserted. For Interrupt-Acknowledge cycles,
Lock will be active for each cycle, and will become
inactive at the end of the first Tc for each cycle
regardless of the number of wait-states inserted.
Instruction Fetching
The M80C286 Bus Unit (BU) will fetch instructions
ahead of the current instruction being executed. This
activity is called prefetching. It occurs when the local
bus would otherwise be idle and obeys the following
rules:
A prefetch bus operation starts when at least two
bytes of the 6-byte prefetch queue are empty.
The prefetcher normally performs word prefetches
independent of the byte alignment of the code segment
base in physical memory.
The prefetcher will perform only a byte code fetch
operation for control transfers to an instruction beginning
on a numerically odd physical address.
Prefetching stops whenever a control transfer or
HLT instruction is decoded by the IU and placed into
the instruction queue.
27
M80C286
In real address mode, the prefetcher may fetch up to
6 bytes beyond the last control transfer or HLT instruction
in a code segment.
In protected mode, the prefetcher will never cause a
segment overrun exception. The prefetcher stops at
the last physical memory word of the code segment.
Exception 13 will occur if the program attempts to
execute beyond the last full instruction in the code
segment.
If the last byte of a code segment appears on an
even physical memory address, the prefetcher will
read the next physical byte of memory (perform a
word code fetch). The value of this byte is ignored
and any attempt to execute it causes exception 13.
271103±27
NOTES:
1. Status lines are not driven by M80C286, yet remain high due to internal pullup resistors during HOLD state. See
section on bus hold circuitry.
2. Address, M/IO and COD/INTA may start floating during any TC depending on when internal M80C286 bus arbiter
decides to release bus to external HOLD. The float starts in w2 of TC . See section on bus hold circuitry.
3. BHE and LOCK may start floating after the end of any TC depending on when internal M80C286 bus arbiter decides
to release bus to external HOLD. The float starts in w1 of TC . See section on bus hold circuitry.
4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other
machine state (i.e., Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous
ready state is ignored after ready is signaled via the asynchronous input.
Figure 29. MULTIBUS Write Terminated by Asynchronous Ready with Bus Hold
28
M80C286
Processor Extension Transfers
The processor extension interface uses I/O port addresses
00F8(H), 00FA(H), and 00FC(H) which are
part of the I/O port address range reserved by Intel.
An ESC instruction with Machine Status Word bits
EM e 0 and TS e 0 will perform I/O bus operations
to one or more of these I/O port addresses independent
of the value of IOPL and CPL.
ESC instructions with memory references enable the
CPU to accept PEREQ inputs for processor extension
operand transfers. The CPU will determine the
operand starting address and read/write status of
the instruction. For each operand transfer, two or
three bus operations are performed, one word transfer
with I/O port address 00FA(H) and one or two
bus operations with memory. Three bus operations
are required for each word operand aligned on an
odd byte address.
NOTE:
Odd-aligned numerics instructions should be avoided
when using an M80C286 system running six or
more memory-write wait-states. The M80C286 can
generate an incorrect numerics address if all the
following conditions are met:
Ð Two floating point (FP) instructions are fetched
and in the M80C286 queue.
Ð The first FP instruction is any floating point store
except FSTSW AX.
Ð The second FP instruction is any floating point
store except FSTSW AX.
Ð The second FP instruction accesses memory.
Ð The operand of the first instruction is aligned on
an odd memory address.
Ð More than five wait-states are inserted during either
of the last two memory write transfers
(transferred as two bytes for odd aligned operands)
of the first instruction.
The second FP instruction operand address will be
incremented by one if these conditions are met.
These conditions are most likely to occur in a multimaster
system. For a hardware solution, contact
your local Intel representative.
Ten or more command delays should not be used
when accessing the numerics coprocessor. Excessive
command delays can cause the M80C286 and
M80C287 to lose synchronization.
Interrupt Acknowledge Sequence
Figure 30 illustrates an interrupt acknowledge sequence
performed by the M80C286 in response to
an INTR input. An interrupt acknowledge sequence
consists of two INTA bus operations. The first allows
a master M8259A Programmable Interrupt Controller
(PIC) to determine which if any of its slaves
should return the interrupt vector. An eight bit vector
is read on D0±D7 of the M80C286 during the second
INTA bus operation to select an interrupt handler
routine from the interrupt table.
The Master Cascade Enable (MCE) signal of the
M82C288 is used to enable the cascade address
drivers, during INTA bus operations (See Figure 30),
onto the local address bus for distribution to slave
interrupt controllers via the system address bus. The
M80C286 emits the LOCK signal (active LOW) during
Ts of the first INTA bus operation. A local bus
``hold'' request will not be honored until the end of
the second INTA bus operation.
Three idle processor clocks are provided by the
M80C286 between INTA bus operations to allow for
the minimum INTA to INTA time and CAS (cascade
address) out delay of the M8259A. The second INTA
bus operation must always have at least one extra
Tc state added via logic controlling READY. This is
needed to meet the M8259A minimum INTA pulse
width.
Local Bus Usage Priorities
The M80C286 local bus is shared among several
internal units and external HOLD requests. In case
of simultaneous requests, their relative priorities are:
(Highest) Any transfers which assert LOCK either
explicitly (via the LOCK instruction prefix)
or implicitly (i.e. some segment descriptor
accesses, interrupt acknowledge sequence,
or an XCHG with memory).
The second of the two byte bus operations
required for an odd aligned word operand.
The second or third cycle of a processor
extension data transfer.
Local bus request via HOLD input.
Processor extension data operand transfer
via PEREQ input.
Data transfer performed by EU as part of
an instruction.
(Lowest) An instruction prefetch request from BU.
The EU will inhibit prefetching two processor
clocks in advance of any data
transfers to minimize waiting by EU for a
prefetch to finish.
29
M80C286
271103±28
NOTES:
1. Data is ignored, upper data bus, D8±D15, should not change state during this time.
2. First INTA cycle should have at least one wait state inserted to meet M8259A minimum INTA pulse width.
3. Second INTA cycle should have at least one wait state inserted to meet M8259A minimum INTA pulse width.
4. LOCK is active for the first INTA cycle to prevent a bus arbiter from releasing the bus between INTA cycles in a multimaster
system. LOCK is also active for the second INTA cycle.
5. A23±A0 exits 3-state OFF during w2 of the second TC in the INTA cycle. See section on bus hold circuitry.
6. Upper data bus should not change state during this time.
Figure 30. Interrupt Acknowledge Sequence
Halt or Shutdown Cycles
The M80C286 externally indicates halt or shutdown
conditions as a bus operation. These conditions occur
due to a HLT instruction or multiple protection
exceptions while attempting to execute one instruction.
A halt or shutdown bus operation is signalled
when S1, S0 and COD/INTA are LOW and M/IO is
HIGH. A1 HIGH indicates halt, and A1 LOW indicates
shutdown. The 82288 bus controller does not
issue ALE, nor is READY required to terminate a halt
or shutdown bus operation.
During halt or shutdown, the M80C286 may service
PEREQ or HOLD requests. A processor extension
segment overrun exception during shutdown will inhibit
further service of PEREQ. Either NMI or RESET
will force the M80C286 out of either halt or shutdown.
An INTR, if interrupts are enabled, or a processor
extension segment overrun exception will also
force the M80C286 out of halt.
30
M80C286
271103±29
Figure 31. Example Power-Down Sequence
THE POWER-DOWN FEATURE OF
THE M80C286
The M80C286, unlike the HMOS part, can enter into
a power-down mode. By stopping the processor
CLK, the processor will enter a power-down mode.
Once in the power-down mode, all M80C286 outputs
remain static (the same state as before the mode
was entered). The M80C286 D.C. specification ICCS
rates the amount of current drawn by the processor
when in the power-down mode. When the CLK is
reapplied to the processor, it will resume execution
where it was interrupted.
In order to obtain maximum benefits from the powerdown
mode, certain precautions should be taken.
When in the power-down mode, all M80C286 outputs
remain static and any output that is turned on
and remains in a HIGH condition will source current
when loaded. Best low-power performance can be
obtained by first putting the processor in the HOLD
condition (turning off all of the output buffers), and
then stopping the processor CLK in the phase 2
state. In this condition, any output that is loaded will
source only the ``Bus Hold Sustaining Current''.
When stopping the processor clock, minimum clock
high and low times cannot be violated (no glitches
on the clock line).
Violating this condition can cause the M80C286 to
erase its internal register states. Note that all inputs
to the M80C286 (CLK, HOLD, PEREQ, RESET,
READY, INTR, NMI, BUSY, and ERROR) should be
at VCC or VSS; any other value will cause the
M80C286 to draw additional current.
When coming out of power-down mode, the system
CLK must be started with the same polarity in which
it was stopped. An example power down sequence
is shown in Figure 31.
BUS HOLD CIRCUITRY
To avoid high current conditions caused by floating
inputs to peripheral CMOS devices and eliminate the
need for pull-up/down resistors, ``bus-hold'' circuitry
has been used on all tri-state M80C286 outputs. See
Table 16 for a list of these pins and Figures 32 and
33 for a complete description of which pins have bus
hold circuitry. These circuits will maintain the last
valid logic state if no driving source is present (i.e.,
an unconnected pin or a driving source which goes
to a high impedance state). To overdrive the ``bus
hold'' circuits, an external driver must be capable of
supplying the maximum ``Bus Hold Overdrive'' sink
or source current at valid input voltage levels. Since
this ``bus hold'' circuitry is active and not a
Pull-Up/Pull-Down
271103±30
Figure 32. Bus Hold Circuitry Pins 36±51, 66±67
31
M80C286
``resistive'' type element, the associated power supply
current is negligible and power dissipation is significantly
reduced when compared to the use of passive
pull-up resistors.
Table 16. Bus Hold Circuitry on the M80C286
Signal
Pin Polarity Pulled to
Location when tri-stated
S1, S0, PEACK, LOCK 4±6, 68 Hi, See Figure 33
Data Bus (D0±D15) 36±51 Hi/Lo,
See Figure 32
COD/INTA, M/IO 66±67 Hi/Lo,
See Figure 32
Pull-Up
271103±31
Figure 33. Bus Hold Circuitry Pins 4±6, 68
SYSTEM CONFIGURATIONS
The versatile bus structure of the M80C286 microsystem,
with a full complement of support chips, allows
flexible configuration of a wide range of systems.
The basic configuration, shown in Figure 34, is
similar to an M8086 maximum mode system. It includes
the CPU plus an M8259A interrupt controller,
M82C284 clock generator, and the M82C288 Bus
Controller.
As indicated by the dashed lines in Figure 34, the
ability to add processor extensions is an integral feature
of M80C286 microsystems. The processor extension
interface allows external hardware to perform
special functions and transfer data concurrent
with CPU execution of other instructions. Full system
integrity is maintained because the M80C286 supervises
all data transfers and instruction execution for
the processor extension.
The M80C287 NPX can perform numeric calculations
and data transfers concurrently with CPU program
execution. Numerics code and data have the
same integrity as all other information protected by
the M80C286 protection mechanism.
The M80C286 can overlap chip select decoding and
address propagation during the data transfer for the
previous bus operation. This information is latched
by ALE during the middle of a Ts cycle. The latched
chip select and address information remains stable
during the bus operation while the next cycle's address
is being decoded and propagated into the system.
Decode logic can be implemented with a high
speed PROM or PAL.
The optional decode logic shown in Figure 32 takes
advantage of the overlap between address and data
of the M80C286 bus cycle to generate advanced
memory and lO-select signals. This minimizes system
performance degradation caused by address
propagation and decode delays. In addition to selecting
memory and I/O, the advanced selects may
be used with configurations supporting local and
system buses to enable the appropriate bus interface
for each bus cycle. The COD/INTA and M/IO
signals are applied to the decode logic to distinguish
between interrupt, I/O, code and data bus cycles.
By adding a bus arbiter, the M80C286 provides a
MULTIBUS system bus interface as shown in Figure
35. The ALE output of the M82C288 for the
MULTIBUS bus is connected to its CMDLY input to
delay the start of commands one system CLK as
required to meet MULTIBUS address and write data
setup times. This arrangement will add at least one
extra Tc state to each bus operation which uses the
MULTIBUS.
A second M82C288 bus controller and additional
latches and transceivers could be added to the local
bus of Figure 35. This configuration allows the
M80C286 to support an on-board bus for local memory
and peripherals, and the MULTIBUS for system
bus interfacing.
32
M80C286
Figure 34. Basic M80C286 System Configuration
271103±32
33
M80C286
271103±33
Figure 35. MULTIBUS System Bus Interface
34
M80C286
271103±34
Figure 36. M80C286 System Configuration with Dual-Ported Memory
Figure 36 shows the addition of dual ported dynamic
memory between the MULTIBUS system bus and
the M80C286 local bus. The dual port interface is
provided by the 8207 Dual Port DRAM Controller.
The 8207 runs synchronously with the CPU to maximize
throughput for local memory references. It also
arbitrates between requests from the local and system
buses and performs functions such as refresh,
initialization of RAM, and read/modify/write cycles.
The 8207 combined with the 8206 Error Checking
and Correction memory controller provide for single
bit error correction. The dual-ported memory can be
combined with a standard MULTIBUS system bus
interface to maximize performance and protection in
multiprocessor system configurations.
Mechanical Data
The M80C286 pinout for both the Ceramic Quad
Flatpack, CQFP, and Pin Grid Array, PGA, packages
are shown in Figure 37. VCC and GND connections
must be made to mutiple VCC and VSS (GND) pins.
Each VCC and VSS MUST be connected to the appropriate
voltage level. The circuit board should include
VCC and GND planes for power distribution
and all VCC pins must be connected to the appropriate
plane.
Table 17 shows the pin assignments for both the
CQFP and PGA components.
NOTE:
Pins identified as ``N.C.'' should remain completely
unconnected.
35
M80C286
Component Pad ViewsÐAs viewed from underside of
component when mounted on the board.
P.C. Board ViewsÐAs viewed from the component
side of the P.C. board.
Ceramic Quad Flatpack
271103±35
NOTE: Pin Grid Array
N.C. signals must not be connected
271103±36
Figure 37. M80C286 Pin Configuration
36
M80C286
Table 17. Pin Cross Reference for M80C286
Signal CQFP PGA
A0 44 34
A1 45 33
A2 46 32
A3 50 28
A4 51 27
A5 52 26
A6 53 25
A7 54 24
A8 55 23
A9 56 22
A10 57 21
A11 58 20
A12 59 19
A13 60 18
A14 61 17
A15 62 16
A16 63 15
A17 64 14
A18 65 13
A19 66 12
A20 67 11
A21 68 10
A22 2 8
Signal CQFP PGA
A23 3 7
D0 42 36
D1 40 38
D2 38 40
D3 36 42
D4 34 44
D5 32 46
D6 30 48
D7 28 50
D8 41 37
D9 39 39
D10 37 41
D11 35 43
D12 33 45
D13 31 47
D14 29 49
D15 27 51
CLK 47 31
RESET 49 29
BHE 9 1
S1 6 4
S0 5 5
PEACK 4 6
Signal CQFP PGA
LOCK 10 68
M/IO 11 67
COD/INTA 12 66
HLDA 13 65
HOLD 14 64
READY 15 63
PEREQ 17 61
NMI 19 59
INTR 21 57
BUSY 24 54
ERROR 25 53
CAP 26 52
VSS 1 9
VSS 18 35
VSS 43 60
VCC 16 30
VCC 48 62
N.C. 7 2
N.C. 8 3
N.C. 20 55
N.C. 22 56
N.C. 23 58
Table 18. Pin Description
The following pin function descriptions are for the M80C286 microprocessor :
Symbol Type Name and Function
CLK I SYSTEM CLOCK provides the fundamental timing for M80C286 systems. It is
divided by two inside the M80C286 to generate the processor clock. The internal
divide-by-two circuitry can be synchronized to an external clock generator by a
LOW to HIGH transition on the RESET input.
D15±D0 I/O DATA BUS inputs data during memory, I/O, and interrupt acknowledge read
cycles; outputs data during memory and I/O write cycles. The data bus is active
HIGH and floats to 3-state OFF* during bus hold acknowledge.
A23±A0 O ADDRESS BUS outputs physical memory and I/O port addresses. A0 is LOW
when data is to be transferred on pins D7±0. A23±A16 are LOW during I/O
transfers. The address bus is active HIGH and floats to 3-state OFF* during bus
hold acknowledge.
BHE O BUS HIGH ENABLE indicates transfer or data on the upper byte of the data bus.
D15±8. Eight-bit oriented devices assigned to the upper byte of the data bus would
normally use BHE to condition chip select functions. BHE is active LOW and floats
to 3-state OFF* during bus hold acknowledge.
*See bus hold circuitry section.
37
M80C286
Table 18. Pin Description (Continued)
Symbol Type Name and Function
BHE BHE and A0 Encodings
(Continued) BHE Value A0 Value Function
0 0 Word transfer
0 1 Transfer on upper half of data bus (D15±D8)
1 0 Byte transfer on lower half of data bus (D7±D0)
1 1 Will never occur
S1, S0 O BUS CYCLE STATUS indicates initiation of a bus cycle and, along with M/IO and COD/
INTA, defines the type of bus cycle. The bus is in a Ts state whenever one or both are LOW,
S1 and S0 are active LOW and float to 3-state OFF* during bus hold acknowledge.
M80C286 Bus Cycle Status Definition
COD/INTA M/IO S1 S0 Bus Cycle Initiated
0 (LOW) 0 0 0 Interrupt acknowledge
0 0 0 1 Will not occur
0 0 1 0 Will not occur
0 0 1 1 None; not a status cycle
0 1 0 0 IF A1 e 1 then halt; else shutdown
0 1 0 1 Memory data read
0 1 1 0 Memory data write
0 1 1 1 None; not a status cycle
1 (HIGH) 0 0 0 Will not occur
1 0 0 1 I/O read
1 0 1 0 I/O write
1 0 1 1 None; not a status cycle
1 1 0 0 Will not occur
1 1 0 1 Memory instruction read
1 1 1 0 Will not occur
1 1 1 1 None; not a status cycle
M/IO O MEMORY I/O SELECT distinguishes memory access from I/O access. If HIGH during Ts, a
memory cycle or a halt/shutdown cycle is in progress. If LOW, an I/O cycle or an interrupt
acknowledge cycle is in progress. M/IO floats to 3-state OFF* during bus hold
acknowledge.
COD/INTA O CODE/INTERRUPT ACKNOWLEDGE distinguishes instruction fetch cycles from memory
data read cycles. Also distinguishes interrupt acknowledge cycles from I/O cycles. COD/
INTA floats to 3-state OFF* during bus hold acknowledge. Its timing is the same as M/IO.
LOCK O BUS LOCK indicates that other system bus masters are not to gain control of the system
bus for the current and the following bus cycle. The LOCK signal may be activated explicitly
by the ``LOCK'' instruction prefix or automatically by M80C286 hardware during memory
XCHG instructions, interrupt acknowledge, or descriptor table access. LOCK is active LOW
and floats to 3-state OFF* during bus hold acknowledge.
READY I BUS READY terminates a bus cycle. Bus cycles are extended without limit until terminated
by READY LOW. READY is an active LOW synchronous input requiring setup and hold
times relative to the system clock be met for correct operation. READY is ignored during
bus hold acknowledge.
HOLD I BUS HOLD REQUEST AND HOLD ACKNOWLEDGE control ownership of the M80C286
HLDA O local bus. The HOLD input allows another local bus master to request control of the local
bus. When control is granted, the M80C286 will float its bus drivers to 3-state OFF* and
then activate HLDA, thus entering the bus hold acknowledge condition. The local bus will
remain granted to the requesting master until HOLD becomes inactive which results in the
M80C286 deactivating HLDA and regaining control of the local bus. This terminates the bus
hold acknowledge condition. HOLD may be asynchronous to the system clock. These
signals are active HIGH.
INTR I INTERRUPT REQUEST requests the M80C286 to suspend its current program execution
and service a pending external request. Interrupt requests are masked whenever the
interrupt enable bit in the flag word is cleared. When the M80C286 responds to an interrupt
request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt vector
that identifies the source of the interrupt. To assure program interruption, INTR must remain
active until the first interrupt acknowledge cycle is completed. INTR is sampled at the
beginning of each processor cycle and must be active HIGH at least two processor cycles
before the current instruction ends in order to interrupt before the next instruction. INTR is
level sensitive, active HIGH, and may be asynchronous to the system clock.
*See bus hold circuitry section.
38
M80C286
Table 18. Pin Description (Continued)
Symbol Type Name and Function
NMI I NON-MASKABLE INTERRUPT REQUEST interrupts the M80C286 with an
internally supplied vector value of 2. No interrupt acknowledge cycles are
performed. The interrupt enable bit in the M80C286 flag word does not affect
this input. The NMI input is active HIGH, may be asynchronous to the system
clock, and is edge triggered after internal synchronization. For proper
recognition, the input must have been previously LOW for at least four system
clock cycles and remain HIGH for at least four system clock cycles.
PEREQ I PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE
PEACK O extend the memory management and protection capabilities of the M80C286
to processor extensions. The PEREQ input requests the M80C286 to perform
a data operand transfer for a processor extension. The PEACK output signals
the processor extension when the requested operand is being transferred.
PEREQ is active HIGH and floats to 3-state OFF* during bus hold
acknowledge. PEACK may be asynchronous to the system clock. PEACK is
active LOW.
BUSY I PROCESSOR EXTENSION BUSY AND ERROR indicate the operating
ERROR I condition of a processor extension to the M80C286. An active BUSY input
stops M80C286 program execution on WAIT and some ESC instructions until
BUSY becomes inactive (HIGH). The M80C286 may be interrupted while
waiting for BUSY to become inactive. An active ERROR input causes the
M80C286 to perform a processor extension interrupt when executing WAIT or
some ESC instructions. These inputs are active LOW and may be
asynchronous to the system clock. These inputs have internal pull-up
resistors.
RESET I SYSTEM RESET clears the internal logic of the M80C286 and is active HIGH.
The M80C286 may be reinitialized at any time with a LOW to HIGH transition
on RESET which remains active for more than 16 system clock cycles. During
RESET active, the output pins of the M80C286 enter the state shown below:
M80C286 Pin State During Reset
Pin Value Pin Names
1 (HIGH) S0, S1, PEACK, A23±A0, BHE, LOCK
0 (LOW) M/IO, COD/INTA, HLDA (Note 1)
3-state OFF* D15±D0
Operation of the M80C286 begins after a HIGH to LOW transition on RESET.
The HIGH to LOW transition of RESET must be synchronous to the system
clock. Approximately 38 CLK cycles from the trailing edge of RESET are
required by the M80C286 for internal initialization before the first bus cycle, to
fetch code from the power-on execution address, occurs.
A LOW to HIGH transition of RESET synchronous to the system clock will
end a processor cycle at the second HIGH to LOW transition of the system
clock. The LOW to HIGH transition of RESET may be asynchronous to the
system clock; however, in this case it cannot be predetermined which phase
of the processor clock will occur during the next system clock period.
Synchronous LOW to HIGH transitions of RESET are required only for
systems where the processor clock must be phase synchronous to another
clock.
VSS I SYSTEM GROUND: 0 Volts.
VCC I SYSTEM POWER: a5 Volt Power Supply.
CAP I SUBSTRATE FILTER CAPACITOR: a 0.047 mF g 20% 12V capacitor can
be connected between this pin and ground for compatibility with the HMOS
M80286. For systems using only an M80C286, this pin can be left floating.
*See bus hold circuitry section.
NOTE:
1. HLDA is only Low if HOLD is inactive (Low).
39
M80C286
Table 19. M80C286 Systems Recommended Pull Up Resistor Values
M80C286 Pin and Name Pullup Value Purpose
4ÐS1
Pull S0, S1, and PEACK inactive during M80C286 hold periods
5ÐS0 20 KX g10%
(Note 1)
6ÐPEACK
63ÐREADY 910X g5%
Pull READY inactive within required minimum time (CL e 150 pF,
lR s 7 mA)
NOTE:
1. Pullup resistors are not required for S0 and S1 when the corresponding pins on the M82C284 are connected to S0 and
S1.
M80286 IN-CIRCUIT EMULATION
CONSIDERATIONS
One of the advantages of using the M80C286 is that
full in-circuit emulation development support is available
thru either the I2ICE 80286 probe for
8 MHz/10 MHz or ICE286 for 12.5 MHz designs. To
utilize these powerful tools it is necessary that the
designer be aware of a few minor parametric and
functional differences between the M80C286 and
the in-circuit emulators. The I2ICE datasheet (I2ICE
Integrated Instrumentation and In-Circuit Emulation
System, order Ý210469) contains a detailed description
of these design considerations. The
ICE286 Fact Sheet (Ý280718) and User's Guide
(Ý452317) contain design considerations for the
80286 12.5 MHz microprocessor. It is recommended
that the appropriate document be reviewed by the
80286 system designer to determine whether or not
these differences affect the design.
PACKAGE THERMAL
SPECIFICATIONS
The M80C286 Microprocessor is specified for operation
when case temperature (TC) is within the range
of b55§C±a125§C. Case temperature, unlike ambient
temperature, is easily measured in any environment
to determine whether the M80C286 Microprocessor
is within the specified operating range. The
case temperature should be measured at the center
of the top surface of the component.
The maximum ambient temperature (TA) allowable
without violating TC specifications can be calculated
from the equations shown below. TJ is the 80C286
junction temperature. P is the power dissipated by
the M80C286.
TJ e TC a P * iJC
TA e TJ b P * iJA
TC e TA a P * [iJA b iJC]
Values for iJA and iJC are given in Table 20. Table
21 shows the maximum TA allowable (without exceeding
TC).
Junction temperature calculations should use an ICC
value that is measured without external resistive
loads. The external resistive loads dissipate additional
power external to the M80C286 and not on
the die. This increases the resistor temperature, not
the die temperature. The full capacitive load (CL e
100 pF) should be applied during the ICC measurement.
Table 20. Thermal Resistances (§C/W)
Package iJC iJC
68-Lead PGA 5.5 30
68-Lead CQFP 11 32
NOTE:
The numbers in Table 20 were calculated using an
ICC of 150 mA, which is representative of the worst
case ICC at TC e 125§C with the outputs unloaded.
Table 21. Maximum (TA)
Package TA (§C)
68-Lead PGA 105
68-Lead CQFP 108
40
M80C286
ABSOLUTE MAXIMUM RATINGS*
Case Temperature under Bias ÀÀÀb55§C to a125§C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀÀb65§C toa150§C
Voltage on Any Pin with
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀb1.0V to a7V
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.1W
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before
finalizing a design.
*WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and extended
exposure beyond the ``Operating Conditions''
may affect device reliability.
Operating Conditions
Symbol Description Min Max Units
TC Case Temperature (Instant On) b55 a125 §C
VCC Digital Supply Voltage 4.50 5.50 V
D.C. CHARACTERISTICS Over Specified Operating Conditions
Symbol Parameter Min Max Unit Comments
ICC Supply Current 200 mA CL e 100 pF (Note 6)
ICCS Supply Current (Static) 5 mA (Note 7)
CCLK CLK Input Capacitance 20 pF FREQ e 1 MHz
CIN Other Input Capacitance 10 pF FREQ e 1 MHz
CO Input/Output Capacitance 20 pF FREQ e 1 MHz
VIL Input LOW Voltage b0.5 0.8 V FREQ e 2 MHz
VIH Input HIGH Voltage 2.0 VCC a 0.5 V FREQ e 2 MHz
VILC CLK Input LOW Voltage b0.5 0.8 V FREQ e 2 MHz
VIHC CLK Input HIGH Voltage 3.8 VCC a 0.5 V FREQ e 2 MHz
VOL Output LOW Voltage 0.45 V IOL e 2.0 mA, FREQ e 2 MHz
VOH Output HIGH Voltage 3.0 V IOHe b2.0 mA, FREQ e 2 MHz
VCC b 0.5 V IOHe b100 mA, FREQ e 2 MHz
ILI Input Leakage Current g10 mA VIN e GND or VCC (Note 6)
ILO Output Leakage Current g10 mA VOeGND or VCC (Note 1)
IIL Input Sustaining Current on b30 b500 mA VIN e 0V (Note 1)
BUSYÝ and ERRORÝ Pins
IBHL Input Sustaining Current 35 200 mA VIN e 1.0V (Notes 1, 2)
(Bus Hold LOW)
IBHH Input Sustaining Current b50 b400 mA VIN e 3.0V (Notes 1, 3)
(Bus Hold HIGH)
IBHLO Bus Hold LOW Overdrive 250 mA (Notes 1, 4)
IBHHO Bus Hold HIGH Overdrive b420 mA (Notes 1, 5)
NOTES:
1. Tested with the clock stopped.
2. IBHL should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36±51, 66, 67.
3. IBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins: 4±6, 36±51, 66±68.
4. An external driver must source at least IBHLO to switch this node from LOW to HIGH.
5. An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
6. Tested with outputs unloaded and at maximum frequency.
7. Tested while clock stopped in phase 2 and inputs at VCC or VSS with the outputs unloaded.
41
M80C286
A.C. CHARACTERISTICS Over Specified Operating Conditions
A.C. timings are referenced to 1.5V points of signals as illustrated in datasheet waveforms, unless otherwise
noted.
Symbol Parameter
10 MHz
Unit Comments
Min Max
1 System Clock (CLK) Period 50 DC ns
2 System Clock (CLK) LOW Time 12 ns at 1.0V
3 System Clock (CLK) HIGH Time 16 ns at 3.6V
17 System Clock (CLK) Rise Time 8 ns 1.0V to 3.6V
18 System Clock (CLK) Fall Time 8 ns 3.6V to 1.0V
4 Asynchronous Inputs Setup Time 20 ns (Note 1)
5 Asynchronous Inputs Hold Time 20 ns (Note 1)
6 RESET Setup Time 23 ns
7 RESET Hold Time 5 ns
8 Read Data Setup Time 8 ns
9 Read Data Hold Time 8 ns
10 READY Setup Time 26 ns
11 READY Hold Time 25 ns
12a1 Status Active Delay 5 22 ns (Notes 2, 3)
12a2 PEACK Active Delay 5 22 ns (Notes 2, 3)
12b Status/PEACK Inactive Delay 3 30 ns (Notes 2, 3)
13 Address Valid Delay 4 35 ns (Notes 2, 3)
14 Write Data Valid Delay 3 40 ns (Notes 2, 3)
15 Address/Status/Data Float Delay 2 47 ns (Notes 2, 4)
16 HLDA Valid Delay 3 47 ns (Notes 2, 3)
19 Address Valid To Status 27 ns (Notes 2, 3)
Valid Setup Time
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing
purposes, to assure recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK, to 1.5V or float on the output as appropriate for valid or floating condition.
3. Output load: CL e 100 pF.
4. Float condition occurs when output current is less than ILO in magnitude.
42
M80C286
A.C. CHARACTERISTICS (Continued)
271103±37
NOTE:
AC Test Loading on Outputs
271103±38
NOTE:
AC Drive and Measurement PointsÐCLK Input
271103±39
NOTE:
AC Setup, Hold and Delay Time MeasurementÐGeneral
43
M80C286
Typical Capacitive Derating Curves
271103±40
Typical CMOS Level Slew Rates for Address/Data Buffers
271103±41
44
M80C286
Typical TTL Level Slew Rates for Address/Data Buffers
271103±42
Typical ICC vs Frequency for Different Output Loads
271103±43
45
M80C286
A.C. CHARACTERISTICS (Continued)
M82C284 Timing Requirements
Symbol Parameter
M82C284-10
Unit Comments
Min Max
11 SRDY/SRDYEN Setup Time 17.5 ns
12 SRDY/SRDYEN Hold Time 2 ns
13 ARDY/ARDYEN Setup Time 0 ns (Note 1)
14 ARDY/ARDYEN Hold Time 30 ns (Note 1)
19 PCLK Delay 0 35 ns CL e 75 pF
IOL e 5 mA
IOHe b1 mA
NOTE:
1. These times are given for testing purposes to assure a predetermined action.
M82C288 Timing Requirements
Symbol Parameter
M82C288-10
Unit Comments
Min Max
12 CMDLY Setup Time 15 ns
13 CMDLY Hold Time 1 ns
30 Command Command Inactive 5 20 CL e 300 pF max
Delay
Command Active 3 21
ns IOL e 32 mA max
29 from CLK IOHe b5 mA max
16 ALE Active Delay 3 16 ns
17 ALE Inactive Delay 19 ns
19 DT/R Read Active Delay 23 ns
22 DT/R Read Inactive Delay 5 20 ns CL e 150 pF
IOL e 16 mA max
20 DEN Read Active Delay 5 21 ns IOHe b1 mA max
21 DEN Read Inactive Delay 3 21 ns
23 DEN Write Active Delay 23 ns
24 DEN Write Inactive Delay 3 19 ns
46
M80C286
WAVEFORMS
MAJOR CYCLE TIMING
271103±44
NOTE:
1. The modified timing is due to the CMDLY signal being active.
47
M80C286
WAVEFORMS (Continued)
M80C286 ASYNCHRONOUS
INPUT SIGNAL TIMING
271103±45
NOTES:
1. PCLK indicates which processor cycle phase will occur
on the next CLK. PCLK may not indicate the correct
phase until the first bus cycle is performed.
2. These inputs are asynchronous. The setup and hold
times shown assure recognition for testing purposes.
M80C286 RESET INPUT TIMING AND
SUBSEQUENT PROCESSOR CYCLE PHASE
271103±46
NOTE:
1. When RESET meets the setup time shown, the next
CLK will start or repeat w2 of a processor cycle.
EXITING AND ENTERING HOLD
271103±47
NOTES:
1. These signals may not be driven by the M80C286 during the time shown. The worst case in terms of latest float time
is shown.
2. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC.
3. The M80C286 floats its status pins during TH. External 20 KX resistors keep these signals high (see Table 16).
4. For HOLD request set up to HLDA, refer to Figure 29.
5. BHE and LOCK are driven at this time but will not become valid until TS.
6. The data bus will remain in 3-state OFF if a read cycle is performed.
48
M80C286
WAVEFORMS (Continued)
M80C286 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
NOTES: 271103±48
1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence.
The first bus operation will be either a memory read at operand address or I/O read at port address OOFA(H).
2. To prevent a second processor extension data operand transfer, the worst case maximum time (Shown above) is:
3cjb12a2max.bmmin.. The actual, configuration dependent, maximum time is: 3cjb12a2max.bmmin. a
Ac2cj.
A is the number of extra TC states added to either the first or second bus operation of the processor extension data
operand transfer sequence.
INITIAL M80C286 PIN STATE DURING RESET
NOTES: 271103±49
1. Setup time for RESET u may be violated with the consideration that w1 of the processor clock may begin one
system CLK period later.
2. Setup and hold times for RESET v must be met for proper operation, but RESET v may occur during w1 or w2.
3. The data bus is only guaranteed to be in 3-state OFF at the time shown.
49
M80C286
271103±50
Figure 35. M80C286 Instruction Format Examples
M80C286 INSTRUCTION SET
SUMMARY
Instruction Timing Notes
The instruction clock counts listed below establish
the maximum execution rate of the M80C286. With
no delays in bus cycles, the actual clock count of an
M80C286 program will average 5% more than the
calculated clock count, due to instruction sequences
which execute faster than they can be fetched from
memory.
To calculate elapsed times for instruction sequences,
multiply the sum of all instruction clock
counts, as listed in the table below, by the processor
clock period. A 10 MHz processor clock has a clock
period of 100 nanoseconds and requires an
M80C286 system clock (CLK input) of 20 MHz.
Instruction Clock Count Assumptions
1. The instruction has been prefetched, decoded,
and is ready for execution. Control transfer instruction
clock counts include all time required to
fetch, decode, and prepare the next instruction for
execution.
2. Bus cycles do not require wait states.
3. There are no processor extension data transfer or
local bus HOLD requests.
4. No exceptions occur during instruction execution.
Instruction Set Summary Notes
Addressing displacements selected by the MOD
field are not shown. If necessary they appear after
the instruction fields shown.
Above/below refers to unsigned value
Greater refers to positive signed value
Less refers to less positive (more negative) signed
values
if d e 1 then to register; if d e 0 then from register
if w e 1 then word instruction; if w e 0 then byte
instruction
if s e 0 then 16-bit immediate data form the operand
if s e 1 then an immediate data byte is sign-extended
to form the 16-bit operand
x don't care
z used for string primitives for comparison with
ZF FLAG
If two clock counts are given, the smaller refers to a
register operand and the larger refers to a memory
operand
* e add one clock if offset calculation requires
summing 3 elements
n e number of times repeated
m e number of bytes of code in next instruction
Level (L)ÐLexical nesting level of the procedure
50
M80C286
The following comments describe possible exceptions,
side effects, and allowed usage for instructions
in both operating modes of the M80C286.
REAL ADDRESS MODE ONLY
1. This is a protected mode instruction. Attempted
execution in real address mode will result in an
undefined opcode exception (6).
2. A segment overrun exception (13) will occur if a
word operand reference at offset FFFF(H) is attempted.
3. This instruction may be executed in real address
mode to initialize the CPU for protected mode.
4. The IOPL and NT fields will remain 0.
5. Processor extension segment overrun interrupt
(9) will occur if the operand exceeds the segment
limit.
EITHER MODE
6. An exception may occur, depending on the value
of the operand.
7. LOCK is automatically asserted regardless of the
presence or absence of the LOCK instruction
prefix.
8. LOCK does not remain active between all operand
transfers.
PROTECTED VIRTUAL ADDRESS MODE ONLY
9. A general protection exception (13) will occur if
the memory operand cannot be used due to either
a segment limit or access rights violation. If
a stack segment limit is violated, a stack segment
overrun exception (12) occurs.
10. For segment load operations, the CPL, RPL, and
DPL must agree with privilege rules to avoid an
exception. The segment must be present to
avoid a not-present exception (11). If the SS register
is the destination, and a segment not-present
violation occurs, a stack exception (12) occurs.
11. All segment descriptor accesses in the GDT or
LDT made by this instruction will automatically
assert LOCK to maintain descriptor integrity in
multiprocessor systems.
12. JMP, CALL, INT, RET, IRET instructions referring
to another code segment will cause a general
protection exception (13) if any privilege rule is
violated.
13. A general protection exception (13) occurs if
CPL i 0.
14. A general protection exception (13) occurs if
CPL l IOPL.
15. The IF field of the flag word is not updated if CPL
l IOPL. The IOPL field is updated only if
CPL e 0.
16. Any violation of privilege rules as applied to the
selector operand do not cause a protection exception;
rather, the instruction does not return a
result and the zero flag is cleared.
17. If the starting address of the memory operand
violates a segment limit, or an invalid access is
attempted, a general protection exception (13)
will occur before the ESC instruction is executed.
A stack segment overrun exception (12) will
occur if the stack limit is violated by the operand's
starting address. If a segment limit is violated
during an attempted data transfer then a
processor extension segment overrun exception
(9) occurs.
18. The destination of an INT, JMP, CALL, RET or
IRET instruction must be in the defined limit of a
code segment or a general protection exception
(13) will occur.
51
M80C286
M80C286 INSTRUCTION SET SUMMARY
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
DATA TRANSFER
MOV eMove:
Register to Register/Memory 1 0 0 0 1 0 0 w mod reg r/m 2,3* 2,3* 2 9
Register/memory to register 1 0 0 0 1 0 1 w mod reg r/m 2,5* 2,5* 2 9
Immediate to register/memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w e 1 2,3* 2,3* 2 9
Immediate to register 1 0 1 1 w reg data data if we1 2 2
Memory to accumulator 1 0 1 0 0 0 0 w addr-low addr-high 5 5 2 9
Accumulator to memory 1 0 1 0 0 0 1 w addr-low addr-high 3 3 2 9
Register/memory to segment register 1 0 0 0 1 1 1 0 mod 0 reg r/m 2,5* 17,19* 2 9,10,11
Segment register to register/memory 1 0 0 0 1 1 0 0 mod 0 reg r/m 2,3* 2,3* 2 9
PUSHePush:
Memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m 5* 5* 2 9
Register 0 1 0 1 0 reg 3 3 2 9
Segment register 0 0 0 reg 1 1 0 3 3 2 9
Immediate 0 1 1 0 1 0 s 0 data data if se0 3 3 2 9
PUSHAePush All 0 1 1 0 0 0 0 0 17 17 2 9
POPePop:
Memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m 5* 5* 2 9
Register 0 1 0 1 1 reg 5 5 2 9
Segment register 0 0 0 reg 1 1 1 (regi01) 5 20 2 9,10,11
POPAePop All 0 1 1 0 0 0 0 1 19 19 2 9
XCHGeExhcange:
Register/memory with register 1 0 0 0 0 1 1 w mod reg r/m 3,5* 3,5* 2,7 7,9
Register with accumulator 1 0 0 1 0 reg 3 3
INeInput from:
Fixed port 1 1 1 0 0 1 0 w port 5 5 14
Variable port 1 1 1 0 1 1 0 w 5 5 14
OUTeOutput to:
Fixed port 1 1 1 0 0 1 1 w port 3 3 14
Variable port 1 1 1 0 1 1 1 w 3 3 14
XLATeTranslate byte to AL 1 1 0 1 0 1 1 1 5 5 9
LEAeLoad EA to register 1 0 0 0 1 1 0 1 mod reg r/m 3* 3*
LDSeLoad pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m (modi11) 7* 21* 2 9,10,11
LESeLoad pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m (modi1) 7* 21* 2 9,10,11
Shaded areas indicate instructions not available in M8086, 88 microsystems.
52
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
DATA TRANSFER (Continued)
LAHF Load AH with flags 1 0 0 1 1 1 1 1 2 2
SAHFeStore AH into flags 1 0 0 1 1 1 1 0 2 2
PUSHFePush flags 1 0 0 1 1 1 0 0 3 3 2 9
POPFePop flags 1 0 0 1 1 1 0 1 5 5 2,4 9,15
ARITHMETIC
ADDeAdd:
Reg/memory with register to either 0 0 0 0 0 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate to register/memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s w e 01 3,7* 3,7* 2 9
Immediate to accumulator 0 0 0 0 0 1 0 w data data if we1 3 3
ADCeAdd with carry:
Reg/memory with register to either 0 0 0 1 0 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate to register/memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s w e 01 3,7* 3,7* 2 9
Immediate to accumulator 0 0 0 1 0 1 0 w data data if we1 3 3
INCeIncrement:
Register/memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m 2,7* 2,7* 2 9
Register 0 1 0 0 0 reg 2 2
SUBeSubtract:
Reg/memory and register to either 0 0 1 0 1 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate from register/memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s w e 01 3,7* 3,7* 2 9
Immediate from accumulator 0 0 1 0 1 1 0 w data data if we1 3 3
SBBeSubtract with borrow:
Reg/memory and register to either 0 0 0 1 1 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate from register/memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s we01 3,7* 3,7* 2 9
Immediate from accumulator 0 0 0 1 1 1 0 w data data if we1 3 3
DECeDecrement
Register/memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m 2,7* 2,7* 2 9
Register 0 1 0 0 1 reg 2 2
CMPeCompare
Register/memory with register 0 0 1 1 1 0 1 w mod reg r/m 2,6* 2,6* 2 9
Register with register/memory 0 0 1 1 1 0 0 w mod reg r/m 2,7* 2,7* 2 9
Immediate with register/memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s we01 3,6* 3,6* 2 9
Immediate with accumulator 0 0 1 1 1 1 0 w data data if we1 3 3
NEGeChange sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m 2 7* 2 9
AAAeASCII adjust for add 0 0 1 1 0 1 1 1 3 3
DAAeDecimal adjust for add 0 0 1 0 0 1 1 1 3 3
53
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
ARITHMETIC (Continued)
AASeASCII adjust for subtract 0 0 1 1 1 1 1 1 3 3
DASeDecimal adjust for subtract 0 0 1 0 1 1 1 1 3 3
MULeMultiply (unsigned): 1 1 1 1 0 1 1 w mod 1 0 0 r/m
Register-Byte 13 13
Register-Word 21 21
Memory-Byte 16* 16* 2 9
Memory-Word 24* 24* 2 9
IMULeInteger multiply (signed): 1 1 1 1 0 1 1 w mod 1 0 1 r/m
Register-Byte 13 13
Register-Word 21 21
Memory-Byte 16* 16* 2 9
Memory-Word 24* 24* 2 9
IMULeInteger immediate multiply 0 1 1 0 1 0 s 1 mod reg r/m data data if s e 0 21,24* 21,24* 2 9
(signed)
DIVeDivide (unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m
Register-Byte 14 14 6 6
Register-Word 22 22 6 6
Memory-Byte 17* 17* 2,6 6,9
Memory-Word 25* 25* 2,6 6,9
IDIVeInteger divide (signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m
Register-Byte 17 17 6 6
Register-Word 25 25 6 6
Memory-Byte 20* 20* 2,6 6,9
Memory-Word 28* 28* 2,6 6,9
AAMeASCII adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 16 16
AADeASCII adjust for divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 14 14
CBWeConvert byte to word 1 0 0 1 1 0 0 0 2 2
CWDeConvert word to double word 1 0 0 1 1 0 0 1 2 2
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1 1 1 0 1 0 0 0 w mod TTT r/m 2,7* 2,7* 2 9
Register/Memory by CL 1 1 0 1 0 0 1 w mod TTT r/m 5an,8an* 5an,8an* 2 9
Register/Memory by Count 1 1 0 0 0 0 0 w mod TTT r/m count 5an,8an* 5an,8an* 2 9
TTT Instruction
0 0 0 ROL
0 0 1 ROR
0 1 0 RCL
0 1 1 RCR
1 0 0 SHL/SAL
1 0 1 SHR
1 1 1 SAR
Shaded areas indicate instructions not available in M8086, 88 microsystems.
54
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
ARITHMETIC (Continued)
ANDeAnd:
Reg/memory and register to either 0 0 1 0 0 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate to register/memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if we1 3,7* 3,7* 2 9
Immediate to accumulator 0 0 1 0 0 1 0 w data data if we1 3 3
TESTeAnd function to flags, no result:
Register/memory and register 1 0 0 0 0 1 0 w mod reg r/m 2,6* 2,6* 2 9
Immediate data and register/memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if we1 3,6* 3,6* 2 9
Immediate data and accumulator 1 0 1 0 1 0 0 w data data if we1 3 3
OReOr:
Reg/memory and register to either 0 0 0 0 1 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate to register/memory 1 0 0 0 0 0 0 w mod 0 0 1 r/m data data if we1 3,7* 3,7* 2 9
Immediate to accumulator 0 0 0 0 1 1 0 w data data if we1 3 3
XOReExclusive or:
Reg/memory and register to either 0 0 1 1 0 0 d w mod reg r/m 2,7* 2,7* 2 9
Immediate to register/memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w e 1 3,7* 3,7* 2 9
Immediate to accumulator 0 0 1 1 0 1 0 w data data if w e1 3 3
NOTeInvert register/memory 1 1 1 1 0 1 1 w mod 0 1 0 r/m 2,7* 2,7* 2 9
STRING MANIPULATION:
MOVSeMove byte/word 1 0 1 0 0 1 0 w 5 5 2 9
CMPSeCompare byte/word 1 0 1 0 0 1 1 w 8 8 2 9
SCASeScan byte/word 1 0 1 0 1 1 1 w 7 7 2 9
LODSeLoad byte/wd to AL/AX 1 0 1 0 1 1 0 w 5 5 2 9
STOSeStor byte/wd from AL/A 1 0 1 0 1 0 1 w 3 3 2 9
INSeInput byte/wd from DX port 0 1 1 0 1 1 0 w 5 5 2 9,14
OUTSeOutput byte/wd to DX port 0 1 1 0 1 1 1 w 5 5 2 9,14
Repeated by count in CX
MOV5eMove string 1 1 1 1 0 0 1 1 1 0 1 0 0 1 0 w 5a4n 5a4n 2 9
CMPSeCompare string 1 1 1 1 0 0 1 z 1 0 1 0 0 1 1 w 5a9n 5a9n 2,8 8,9
SCASeScan string 1 1 1 1 0 0 1 z 1 0 1 0 1 1 1 w 5a8n 5a8n 2,8 8,9
LODSeLoad string 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 w 5a4n 5a4n 2,8 8,9
STOSeStore string 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 w 4a3n 4a3n 2,8 8,9
INSeInput string 1 1 1 1 0 0 1 1 0 1 1 0 1 1 0 w 5a4n 5a4n 2 9,14
OUTSeOutput string 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 w 5a4n 5a4n 2 9,14
Shaded areas indicate instructions not available in M8086, 88 microsystems.
55
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
CONTROL TRANSFER
CALL eCall:
Direct within segment 1 1 1 0 1 0 0 0 disp-low disp-high 7am 7am 2 18
Register/memory 1 1 1 1 1 1 1 1 mod 0 1 0 r/m 7 am, 11am* 7am, 11am* 2,8 8,9,18
indirect within segment
Direct intersegment 1 0 0 1 1 0 1 0 segment offset 13am 26am 2 11,12,18
Protected Mode Only (Direct intersegment): segment selector
Via call gate to same privilege level 41am 8,11,12,18
Via call gate to different privilege level, no parameters 82am 8,11,12,18
Via call gate to different privilege level, x parameters 86 a4xam 8,11,12,18
Via TSS 177am 8,11,12,18
Via task gate 182am 8,11,12,18
Indirect intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m (modi11) 16am 29am* 2 8,9,11,12,18
Protected Mode Only (Indirect intersegment):
Via call gate to same privilege level 44am* 8,9,11,12,18
Via call gate to different privilege level, no parameters 83 am* 8,9,11,12,18
Via call gate to different privilege level, x parameters 90a4x am* 8,9,11,12,18
Via TSS 180am* 8,9,11,12,18
Via task gate 185am* 8,9,11,12,18
JMPeUnconditional jump:
Short/long 1 1 1 0 1 0 1 1 disp-low 7am 7am 18
Direct within segment 1 1 1 0 1 0 0 1 disp-low disp-high 7am 7am 18
Register/memory indirect within segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m 7 am, 11am* 7am, 11am* 2 9,18
Direct intersegment 1 1 1 0 1 0 1 0 segment offset 11am 23am 11,12,18
Protected Mode Only (Direct intersegment): segment selector
Via call gate to same privilege level 38am 8,11,12,18
Via TSS 175am 8,11,12,18
Via task gate 180am 8,11,12,18
Indirect intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m (modi11) 15am* 26am* 2 8,9,11,12,18
Protected Mode Only (Indirect intersegment):
Via call gate to same privilege level 41am* 8,9,11,12,18
Via TSS 178am* 8,9,11,12,18
Via task gate 183am* 8,9,11,12,18
RETeReturn from CALL:
Within segment 1 1 0 0 0 0 1 1 11am 11am 2 8,9,18
Within seg adding immed to SP 1 1 0 0 0 0 1 0 data-low data-high 11am 11am 2 8,9,18
Intersegment 1 1 0 0 1 0 1 1 15am 25am 2 8,9,11,12,18
Intersegment adding immediate to SP 1 1 0 0 1 0 1 0 data-low data-high 15am 2 8,9,11,12,18
Protected Mode Only (RET):
To different privilege level 55am 9,11,12,18
56
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
CONTROL TRANSFER (Continued)
JE/JZeJump on equal zero 0 1 1 1 0 1 0 0 disp 7am or 3 7am or 3 18
JL/JNGEeJump on less/not greater or equal 0 1 1 1 1 1 0 0 disp 7am or 3 7am or 3 18
JLE/JNGeJump on less or equal/not greater 0 1 1 1 1 1 1 0 disp 7am or 3 7am or 3 18
JB/JNAEeJump on below/not above or equal 0 1 1 1 0 0 1 0 disp 7am or 3 7am or 3 18
JBE/JNAeJump on below or equal/not above 0 1 1 1 0 1 1 0 disp 7am or 3 7am or 3 18
JP/JPEeJump on parity/parity even 0 1 1 1 1 0 1 0 disp 7am or 3 7am or 3 18
JOeJump on overflow 0 1 1 1 0 0 0 0 disp 7 am or 3 7am or 3 18
JSeJump on sign 0 1 1 1 1 0 0 0 disp 7a m or 3 7am or 3 18
JNE/JNZeJump on not equal/not zero 0 1 1 1 0 1 0 1 disp 7am or 3 7am or 3 18
JNL/JGEeJump on not less/greater or equal 0 1 1 1 1 1 0 1 disp 7am or 3 7am or 3 18
JNLE/JGeJump on not less or equal/greater 0 1 1 1 1 1 1 1 disp 7am or 3 7am or 3 18
JNB/JAEeJump on not below/above or equal 0 1 1 1 0 0 1 1 disp 7am or 3 7am or 3 18
JNBE/JAeJump on not below or equal/above 0 1 1 1 0 1 1 1 disp 7am or 3 7am or 3 18
JNP/JPOeJump on not par/par odd 0 1 1 1 1 0 1 1 disp 7am or 3 7am or 3 18
JNOeJump on not overflow 0 1 1 1 0 0 0 1 disp 7am or 3 7am or 3 18
JNSeJump on not sign 0 1 1 1 1 0 0 1 disp 7 am or 3 7am or 3 18
LOOPeLoop CX times 1 1 1 0 0 0 1 0 disp 8 am or 4 8am or 4 18
LOOPZ/LOOPEeLoop while zero/equal 1 1 1 0 0 0 0 1 disp 8am or 4 8am or 4 18
LOOPNZ/LOOPNEeLoop while not zero/equal 1 1 1 0 0 0 0 0 disp 8am or 4 8am or 4 18
JCXZeJump on CX zero 1 1 1 0 0 0 1 1 disp 8 am or 4 8am or 4 18
ENTEReEnter Procedure 1 1 0 0 1 0 0 0 data-low data-high L
2,8 8,9
Le0 11 11
2,8 8,9
Le1 15 15
2,8 8,9
L l 1 16a4(L b 1) 16a4(L b 1)
2,8 8,9
LEAVEeLeave Procedure 1 1 0 0 1 0 0 1 5 5
INTeInterrupt:
Type specified 1 1 0 0 1 1 0 1 type 23am 2,7,8
Type 3 1 1 0 0 1 1 0 0 23am 2,7,8
INTOeInterrupt on overflow 1 1 0 0 1 1 1 0 24 am or 3 2,6,8
(3 if no (3 if no
interrupt) interrupt)
Shaded areas indicate instructions not available in M8086, 88 microsystems.
57
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
CONTROL TRANSFER (Continued)
Protected Mode Only:
Via interrupt or trap gate to same privilege level 40a m 7,8,11,12,18
Via interrupt or trap gate to fit different privilege level 78a m 7,8,11,12,18
Via Task Gate 167am 7,8,11,12,18
IRETeInterrupt return 1 1 0 0 1 1 1 1 17am 31am 2,4 8,9,11,12,15,18
Protected Mode Only:
To different privilege level 55am 8,9,11,12,15,18
To different task (NTe1) 169am 8,9,11,12,18
BOUNDeDetect value out of range 0 1 1 0 0 0 1 0 mod reg r/m 13* 13* 2,6 6,8,9,11,12,18
(Use INT clock
count if
exception 5)
PROCESSOR CONTROL
CLCeClear carry 1 1 1 1 1 0 0 0 2 2
CMCeComplement carry 1 1 1 1 0 1 0 1 2 2
STCeSet carry 1 1 1 1 1 0 0 1 2 2
CLDeClear direction 1 1 1 1 1 1 0 0 2 2
STDeSet direction 1 1 1 1 1 1 0 1 2 2
CLIeClear interrupt 1 1 1 1 1 0 1 0 3 3 14
STIeSet interrupt 1 1 1 1 1 0 1 1 2 2 14
HLTeHalt 1 1 1 1 0 1 0 0 2 2 13
WAITeWait 1 0 0 1 1 0 1 1 3 3
LOCKeBus lock prefix 1 1 1 1 0 0 0 0 0 0 14
CTSeClear task switched flag 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 2 2 3 13
ESCeProcessor Extension Escape 1 1 0 1 1 T T T mod LLL r/m 9±20* 9±20* 5,8 8,17
(TTT LLL are opcode to processor extension)
SEGeSegment Override Prefix 001 reg 110 0 0
PROTECTION CONTROL
LGDTeLoad global descriptor table register 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 0 1 0 r/m 11* 11* 2,3 9,13
SGDTeStore global descriptor table register 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 0 0 0 r/m 11* 11* 2,3 9
LIDTeLoad interrupt descriptor table register 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 0 1 1 r/m 12* 12* 2,3 9,13
SIDTeStore interrupt descriptor table register 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 0 0 1 r/m 12* 12* 2,3 9
LLDTeLoad local descriptor table register
from register memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 0 1 0 r/m 17,19* 1 9,11,13
SLDTeStore local descriptor table register
to register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 0 0 0 r/m 2,3* 1 9
Shaded areas indicate instructions not available in M8086, 88 microsystems.
58
M80C286
M80C286 INSTRUCTION SET SUMMARY (Continued)
CLOCK COUNT COMMENTS
Real
Protected
Real
Protected
FUNCTION FORMAT
Address
Virtual
Address
Virtual
Mode
Address
Mode
Address
Mode Mode
PROTECTION CONTROL (Continued)
LTReLocal task register
from register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 0 1 1 r/m 17,19* 1 9,11,13
STReStore task register
to register memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 0 0 1 r/m 2,3* 1 9
LMSWeLoad machine status word
from register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 1 1 0 r/m 3,6* 3,6* 2,3 9,13
SMSWeStore machine status word 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 mod 1 0 0 r/m 2,3* 2,3* 2,3 9
LAReLoad access rights
from register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 mod reg r/m 14,16* 1 9,11,16
LSLeLoad segment limit
from register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 mod reg r/m 14,16* 1 9,11,16
ARPLeAdjust requested privilege level: 0 1 1 0 0 0 1 1 mod reg r/m 10*,11* 2 8,9
from register/memory
VERReVerify read access: register/memory 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 1 0 0 r/m 14,16* 1 9,11,16
VERReVerify write access: 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 mod 1 0 1 r/m 14,16* 1 9,11,16
Shaded areas indicate instructions not available in M8086, 88 microsystems.
59
M80C286
Footnotes
The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:
if mod e 11 then r/m is treated as a REG field
if mod e 00 then DISP e 0*, disp-low and disp-high
are absent
if mod e 01 then DISP e disp-low sign-extended to
16 bits, disp-high is absent
if mod e 10 then DISP e disp-high: disp-low
if r/m e 000 then EA e (BX) a (SI) a DISP
if r/m e 001 then EA e (BX) a (DI) a DISP
if r/m e 010 then EA e (BP) a (SI) a DISP
if r/m e 011 then EA e (BP) a (DI) a DISP
if r/m e 100 then EA e (SI) a DISP
if r/m e 101 then EA e (DI) a DISP
if r/m e 110 then EA e (BP) a DISP*
if r/m e 111 then EA e (BX) a DISP
DISP follows 2nd byte of instruction (before data if
required)
*except if mod e 00 and r/m e 110 then EQ e disp-high: disp-low.
SEGMENT OVERRIDE PREFIX
0 0 1 reg 1 1 0
reg is assigned according to the following:
Segment
reg Register
00 ES
01 CS
10 SS
11 DC
REG is assigned according to the following table:
16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
101 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed
by the BP register are computed using the SS segment
register. The physical addresses of the destination
operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.
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Reference Number: 322911-003
Intel® Core™ i5-600, i3-500
Desktop Processor Series and
Intel® Pentium Processor G6950
Specification Update
March 2010
Revision -003
2
Specification Update
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
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*Other names and brands may be claimed as the property of others.
Copyright © 2010, Intel Corporation. All Rights Reserved.
Contents
3
Specification Update
Contents
Revision History...............................................................................................................5
Preface ..............................................................................................................................6
Summary Tables of Changes..........................................................................................8
Identification Information ..............................................................................................16
Errata ...............................................................................................................................18
Specification Changes...................................................................................................43
Specification Clarifications ...........................................................................................44
Documentation Changes...............................................................................................45
§
Contents
4
Specification Update
5
Specification Update
Revision History
Revision Description Date
-001 Initial Release January 2010
-002
Added Errata AAU85-AAU87.
Corrected Extended Model and Model Number register values in Component Identification
table.
February 2010
-003
Added Errata AAU88-AAU91.
Added Documentation Changes AAU1-AAU3.
March 2010
6
Specification Update
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Related Documents
Document Title Document
Number
Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 1 322909-001
Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2 322910-001
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID Instruction http://www.intel.com/
design/processor/
applnots/241618.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel® 64 and IA-32 Intel Architecture Optimization Reference
Manual
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes
http://www.intel.com/
design/processor/
specupdt/252046.htm
ACPI Specifications www.acpi.info
7
Specification Update
Nomenclature
Errata are design defects or errors. These may cause the processor behavior to
deviate from published specifications. Hardware and software designed to be used with
any given stepping must assume that all errata documented for that stepping are
present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics such as, core speed, L2 cache size,
package type, etc. as described in the processor identification information table. Read
all notes associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
8
Specification Update
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of a table row indicates this erratum is either new or modified from
the previous version of the document.
9
Specification Update
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading technology on 90-
nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel® processor
A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme
Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000
and E4000 sequence
10
Specification Update
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad
processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AU = Intel® Celeron® dual-core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000
series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process
AAA= Intel® Xeon® processor 3300 series
AAB= Intel® Xeon® E3110 processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme processor QX9775
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ processor 300 series
AAI = Intel® Xeon® processor 7400 series
AAJ = Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900
desktop processor series
AAK= Intel® Xeon® processor 5500 series
AAL = Intel® Pentium® dual-core processor E5000 series
AAN = Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950
AAO = Intel® Xeon® processor 3400 series
AAP = Intel® Core™ i7-900 mobile processor Extreme Edition series, Intel Core i7-800 and i7-700
mobile processor series
AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 mobile processor series
AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor
G6950
11
Specification Update
Errata (Sheet 1 of 4)
Number
Steppings
Status ERRATA
C-2
AAU1 X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAU2 X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations
AAU3 X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack
AAU4 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAU5 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AAU6 X No Fix MOV To/From Debug Registers Causes Debug Exception
AAU7 X No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
AAU8 X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
AAU9 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
AAU10 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAU11 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AAU12 X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
Preempted
AAU13 X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
AAU14 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs
in 64-bit Mode
AAU15 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
Error
AAU16 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
AAU17 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAU18 X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
AAU19 X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy
Counter may be Incorrect
AAU20 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAU21 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAU22 X No Fix #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not
Provide Correct Exception Error Code
AAU23 X No Fix Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is
Set on a #GP Instruction
AAU24 X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point
Exception
AAU25 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1
AAU26 X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not
Work
12
Specification Update
AAU27 X No Fix? Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in
Stuck Core Operating Ratio
AAU28 X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an
Unexpected Interrupt
AAU29 X No Fix xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in
Periodic Mode
AAU30 X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced
Data Structures
AAU31 X No Fix Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
Ordering Violations
AAU32 X No Fix Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write
Major Mode Enabled
AAU33 X Plan Fix Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted
RIP onto the Stack
AAU34 X No Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is
Received while All Cores in C6
AAU35 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
AAU36 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt
Service Routine
AAU37 X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
AAU38 X No Fix APIC Error “Received Illegal Vector” May be Lost
AAU39 X No Fix DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/
m or POP SS is a Store
AAU40 X No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a
System Hang
AAU41 X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
AAU42 X No Fix Performance Monitor Counter INST_RETIRED.STORES May Count Higher than
Expected
AAU43 X No Fix Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using
Destination Field Instead of Shorthand
AAU44 X No Fix Faulting Executions of FXRSTOR May Update State Inconsistently
AAU45 X No Fix Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is
Disable
AAU46 X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
AAU47 X No Fix Performance Monitor Counters May Count Incorrectly
AAU48 X No Fix Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores
to Local DRAM Correctly
AAU49 X No Fix EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
Translation Change
AAU50 X No Fix Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
AAU51 X No Fix Corrected Errors With a Yellow Error Indication May be Overwritten by Other
Corrected Errors
Errata (Sheet 2 of 4)
Number
Steppings
Status ERRATA
C-2
13
Specification Update
AAU52 X No Fix Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST
May Overcount
AAU53 X No Fix Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior
AAU54 X No Fix APIC Timer CCR May Report 0 in Periodic Mode
AAU55 X No Fix Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May
Count Inaccurately
AAU56 X No Fix A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or
PDPTE
AAU57 X No Fix BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-SIPI
Sequence
AAU58 X No Fix Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
AAU59 X No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
AAU60 X No Fix The Memory Controller tTHROT_OPREF Timings May be Violated During Self
Refresh Entry
AAU61 X No Fix VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI
Blocking
AAU62 X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
AAU63 X No Fix LBRs May Not be Initialized During Power-On Reset of the Processor
AAU64 X No Fix LBR, BTM or BTS Records May have Incorrect Branch From Information After an
EIST Transition, T-states, C1E, or Adaptive Thermal Throttling
AAU65 X No Fix VMX-Preemption Timer Does Not Count Down at the Rate Specified
AAU66 X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter
0
AAU67 X No Fix VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size
AAU68 X No Fix Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
AAU69 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
AAU70 X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions
AAU71 X No Fix INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a
Large Page
AAU72 X No Fix Logical Processor May Use Incorrect VPID after VM Entry That Returns From SMM
AAU73 X No Fix The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors
Occurring on Both Channels in Mirror Channel Mode
AAU74 X No Fix MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core
Ratio Multipliers for Non-Existent Core Configurations
AAU75 X Plan Fix Internal Parity Error May Be Incorrectly Signaled during C6 Exit
AAU76 X No Fix PMIs during Core C6 Transitions May Cause the System to Hang
AAU77 X No Fix 2MB Page Split Lock Accesses Combined With Complex Internal Events May
Cause Unpredictable System Behavior
Errata (Sheet 3 of 4)
Number
Steppings
Status ERRATA
C-2
14
Specification Update
AAU78 X No Fix
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is
possible that the APIC timer will deliver two interrupts.
AAU79 X Plan Fix TXT.PUBLIC.KEY is Not Reliable
AAU80 X Plan Fix 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt
Acknowledge Cycle From the Preceding Interrupt
AAU82 X No Fix The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer
is Still Running
AAU83 X No Fix Secondary PCIe Port May Not Train After A Warm Reset
AAU84 X No Fix The PECI Bus May Be Tri-stated after System Reset
AAU85 X No Fix The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
AAU86 X No Fix Processor Hangs on Package C6 State Exit
AAU87 X No Fix A Synchronous SMI May be Delayed
AAU88 X No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
AAU89 X Plan Fix PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/
s
AAU90 X No Fix PCI Express Cards May Not Train to x16 Link Width
AAU91 X No Fix Unexpected Graphics VID Transition During Warm Reset May Cause the System to
Hang
Specification Changes
Number SPECIFICATION CHANGES
None for this revision of this specification update.
Specification Clarifications
Number SPECIFICATION CLARIFICATIONS
None for this revision of this specification update.
Errata (Sheet 4 of 4)
Number
Steppings
Status ERRATA
C-2
15
Specification Update
Documentation Changes
Number DOCUMENTATION CHANGES
AAU1
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add PEG_TC—PCI Express Completion
Timeout RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2 to add PEG_TC—PCI Express Completion Timeout Register
AAU2
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add SSKPD—Sticky Scratchpad Data
RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950
Datasheet, Volume 2 to add PEG_TC—PCI Express Completion Timeout to add SSKPD—Sticky Scratchpad Data
Register
AAU3
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add MCSAMPML—Memory Configuration,
System Address Map and Pre-allocated Memory Lock RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop
Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volume 2 to add MCSAMPML—Memory
Configuration, System Address Map and Pre-allocated Memory Lock Register
16
Specification Update
Identification Information
Component Identification using Programming Interface
The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 stepping can be identified by the following register contents:
Note:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],
to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,
or Intel® Core™ processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are
used to identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM
processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor
system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of
the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the
Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor
stepping ID number in the CPUID information.
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended
Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID
value in the EAX register. Note that the EDX processor signature value after reset is
equivalent to the processor signature output value in the EAX register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 can be identified by the following register contents:
Notes:
1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI
function 0 configuration space.
2. The Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in
the PCI function 0 configuration space.
3. The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI
function 0 configuration space.
Reserved Extended
Family1
Extended
Model2 Reserved Processor
Type3
Family
Code4
Model
Number5
Stepping
ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0010b 00b 0110 0101b xxxxb
Stepping Vendor ID1 Device ID2 Revision ID3
C-2 8086h 0040h 12h
17
Specification Update
Component Marking Information
The processor stepping can be identified by the following component markings.
Notes:
1. This processor has TDP of 73 W.
2. This column indicates maximum Intel® Turbo Boost Technology frequency (GHz) for 2 or 1 cores active
respectively.
3. Intel® Hyper-Threading Technology enabled.
4. Intel® Trusted Execution Technology (Intel® TXT) enabled.
5. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.
6. Intel® Virtualization Technology for Directed I/O (Intel® VT-d) enabled.
7. Intel® AES-NI enabled.
8. Intel SSE4.1 and SSE4.2 enabled.
9. This processor has TDP of 87 W.
10. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example,
core frequency of 3.4666, repeating 6, is reported as @3.47 in brand string. Core frequency of 3.3333,
is reported as @3.33 in brand string.)
Figure 1. Processor Production Top-side Markings (Example)
Table 1. Processor Identification
S-Spec
Number
Processor
Number Stepping Processor
Signature
Core Frequency
(GHz) /
DDR3 (MHz) /
Integrated
Graphics
Frequency
Max Intel®
Turbo Boost
Technology
Frequency
(GHz)2
Shared
L3 Cache
Size (MB)
Notes
LBLT i5-670 C-2 20652h 3.46 / 1333 / 733
2 core: 3.60
1 core: 3.73
4
1, 3, 4, 5, 6,
7, 8, 11
LBNE i5-661 C-2 20652h 3.33 / 1333 / 900
2 core: 3.46
1 core: 3.60
4
3, 5, 7, 8, 9,
11
LBLV i5-660 C-2 20652h 3.33 / 1333 / 733
2 core: 3.46
1 core: 3.60
4
1, 3, 4, 5, 6,
7, 8, 11
LBLK i5-650 C-2 20652h 3.20 / 1333 / 733
2 core: 3.33
1 core: 3.46
4
1, 3, 4, 5, 6,
7, 8, 11
LBMQ i3-540 C-2 20652h 3.06 / 1333 / 733 N/A 4
1, 3, 5, 8,
11
LBLR i3-530 C-2 20652h 2.93 / 1333 / 733 N/A 4
1, 3, 5, 8,
11
LBMS G6950 C-2 20652h 2.80 / 1066 / 533 N/A 3 1, 5, 11
LOT NO S/N
INTEL ©'08 PROC#
BRAND
SLxxx [COO]
SPEED/CACHE/FMB
[FPO]
M
e4
18
Specification Update
Errata
AAU1. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the Software Developers Manual section "Outof-
Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.
19
Specification Update
AAU3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong
Address onto the Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a noncanonical
address, the address pushed onto the stack for this #GP fault may not match
the non-canonical address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commerciallyavailable
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU4. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU5. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: If any of the below circumstances occur, it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
• If an instruction that performs a memory load causes a code segment limit
violation.
• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Topof-
Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, or from the
restart and subsequent re-execution of that instruction by the exception handler. If the
target of the load is to uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the repetition of the sideeffect.
Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register
operands may issue a memory load before getting the DNA exception.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
20
Specification Update
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU6. MOV To/From Debug Registers Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU8. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also be
incorrect.
Problem: Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
21
Specification Update
AAU9. Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem: In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
• #DB is signaled before the pending higher priority #MF (Interrupt 16)
• #DB is generated twice on the same instruction
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU10. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e., residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Refer to "Procedure Calls For Block-Structured Languages" in IA-32 Intel®
Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on
the usage of the ENTER instructions. This erratum is not expected to occur in Ring 3.
Faults are usually processed in Ring 0 and stack switch occurs when transferring to
Ring 0. Intel has not observed this erratum on any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU11. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Tables of Changes.
22
Specification Update
AAU12. General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP
fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)).
However, if the preempting lower priority faults are resolved by the operating system
and the instruction retried, a #GP fault will occur.
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are
placed before the instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU13. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that
occur above the 4-G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP
fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the
4-G limit (0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AAU14. LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,
during a specific boundary condition where the exception/interrupt occurs right after
the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)
in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63
to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which
report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/
interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU15. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the
Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error
code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status
register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate
indication of multiple occurrences of DTLB errors. There is no other impact to normal
processor functionality.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
23
Specification Update
AAU16. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
Problem: When a debug exception is signaled on a load that crosses cache lines with data
forwarded from a store and whose corresponding breakpoint enable flags are disabled
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the
corresponding breakpoint enable flag in DR7 is disabled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU17. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local
xAPIC's address space, the processor will hang.
Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space
must be uncached. The MONITOR instruction only functions correctly if the specified
linear address range is of the type write-back. CLFLUSH flushes data from the cache.
Intel has not observed this erratum with any commercially-available software.
Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU18. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first FAR JMP, the subsequent RSM (Resume from System
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software
Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU19. Performance Monitoring Events for Read Miss to Level 3 Cache Fill
Occupancy Counter may be Incorrect
Problem: Whenever an Level 3 cache fill conflicts with another request's address, the miss to fill
occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H), will provide erroneous
results.
Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS event may count a value
higher than expected. The extent to which the value is higher than expected is
determined by the frequency of the L3 address conflict.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
24
Specification Update
AAU20. A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware
as Armed
Problem: A processor write to the address range armed by the MONITOR instruction may not
immediately trigger the monitoring hardware. Consequently, a VM exit on a later
MWAIT may incorrectly report the monitoring hardware as armed, when it should be
reported as unarmed due to the write occurring prior to the MWAIT.
Implication: If a write to the range armed by the MONITOR instruction occurs between the
MONITOR and the MWAIT, the MWAIT instruction may start executing before the
monitoring hardware is triggered. If the MWAIT instruction causes a VM exit, this could
cause its exit qualification to incorrectly report 0x1. In the recommended usage model
for MONITOR/MWAIT, there is no write to the range armed by the MONITOR instruction
between the MONITOR and the MWAIT.
Workaround: Software should never write to the address range armed by the MONITOR instruction
between the MONITOR and the subsequent MWAIT.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU21. Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
Problem: The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts
instructions that load new values into segment registers. The value of the count may be
inaccurate.
Implication: The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or
lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU22. #GP on Segment Selector Descriptor that Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
Problem: During a #GP (General Protection Exception), the processor pushes an error code on to
the exception handler’s stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Status: An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU23. Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
Problem: While coming out of cold reset or exiting from C6, if the processor encounters an
instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is
enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly
logged resulting in an MCE (Machine Check Exception).
Implication: When this erratum occurs, an MCE may be incorrectly signaled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
25
Specification Update
AAU24. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the sequential
execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an
invalid stack during interrupt handling. However, an enabled debug breakpoint or single
step trap may be taken after MOV SS/POP SS if this instruction is followed by an
instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP
instruction. This results in a debug exception being signaled on an unexpected
instruction boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially-available
software or system.
Workaround: As recommended in the IA32 Intel® Architecture Software Developer’s Manual, the use
of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since
the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of
debug tools should be aware of the potential incorrect debug event signaling created by
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU25. IA32_MPERF Counter Stops Counting During On-Demand TM1
Problem: According to the Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to
IA32_APERF (MSR E8H) should reflect actual performance while TM1 or on-demand
throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while TM1
or on-demand throttling is activated, and the ratio of the two will indicate higher
processor performance than actual.
Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state
(performance state) management algorithms under the conditions described above. It
is possible for the Operating System to observe higher processor utilization than actual,
which could lead the OS into raising the P-state. During TM1 activation, the OS P-state
request is irrelevant and while on-demand throttling is enabled, it is expected that the
OS will not be changing the P-state. This erratum should result in no practical
implication to software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU26. Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
Problem: When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
26
Specification Update
AAU27. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,
May Result in Stuck Core Operating Ratio
Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.
Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within
specification, this erratum should never be seen during normal operation.
Workaround: Software should not disable Thermal Monitor during processor operation.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU28. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU29. xAPIC Timer May Decrement Too Quickly Following an Automatic
Reload While in Periodic Mode
Problem: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Implication: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
27
Specification Update
AAU30. Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due
to this erratum, a VMX access to the VMCS or referenced data structures will instead
use the memory type that the MTRRs (memory-type range registers) specify for the
physical address of the access.
Implication: Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type
will be used but the processor may use a different memory type.
Workaround: Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU31. Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Problem: Under complex microarchitectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Implication: Memory ordering may be violated. Intel has not observed this erratum with any
commercially-available software.
Workaround: Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU32. Critical ISOCH Traffic May Cause Unpredictable System Behavior When
Write Major Mode Enabled
Problem: Under a specific set of conditions, critical ISOCH (isochronous) traffic may cause
unpredictable system behavior with write major mode enabled.
Implication: Due to this erratum unpredictable system behavior may occur.
Workaround: Write major mode must be disabled in the BIOS by writing the write major mode
threshold value to its maximum value of 1FH in ISOCHEXITTRESHOLD bits [19:15],
ISOCHENTRYTHRESHOLD bits [14:10], WMENTRYTHRESHOLD bits [9:5], and
WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0,1,2}_WAQ_PARAMS register.
Status: For the steppings affected, see the Summary Tables of Changes.
28
Specification Update
AAU33. Delivery of Certain Events Immediately Following a VM Exit May Push
a Corrupted RIP onto the Stack
Problem: If any of the following events is delivered immediately following a VM exit to 64-bit
mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may
be cleared to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction fetch; or
• A general-protection exception (#GP) due to an attempt to decode an instruction
whose length is greater than 15 bytes.
Implication: Unexpected behavior may occur due to the incorrect value of the RIP on the stack.
Specifically, return from the event handler via IRET may encounter an unexpected page
fault or may begin fetching from an unexpected code address.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU34. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
Problem: If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially-available
software/system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU35. Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem: If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power Cstate,
the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
29
Specification Update
AAU36. EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem: If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI register, the core may not send an EOI transaction (if needed) and further
interrupts from the same priority level or lower may be blocked.
Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt
service routines. Intel has not observed this erratum with any commercially-available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU37. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS
During SMM
Problem: In general, a PEBS record should be generated on the first count of the event after the
counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR
1D9H, bit [14]) prevents performance counters from counting during SMM (System
Management Mode). Due to this erratum, if
1. A performance counter overflowed before an SMI
2. A PEBS record has not yet been generated because another count of the event has
not occurred
3. The monitored event occurs during SMM
then a PEBS record will be saved after the next RSM instruction.
When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event
occurs outside of SMM.
Implication: A PEBS record may be saved after an RSM instruction due to the associated
performance counter detecting the monitored event during SMM; even when
FREEZE_WHILE_SMM is set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU38. APIC Error “Received Illegal Vector” May be Lost
Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error
Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error
is received on the same internal clock that the ESR is being written (as part of the
write-read ESR access flow). The corresponding error interrupt will also not be
generated for this case.
Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR
properly and may not generate an error interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
30
Specification Update
AAU39. DR6 May Contain Incorrect Information When the First Instruction
After a MOV SS,r/m or POP SS is a Store
Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused
by the previous instruction. However, the instruction following a MOV SS,r/m (MOV to
the stack segment selector) or POP SS (POP stack segment selector) instruction will not
clear the changes in DR6 because data breakpoints are not taken immediately after a
MOV SS,r/m or POP SS instruction. Due to this erratum, any DR6 changes caused by a
MOV SS,r/m or POP SS instruction may be cleared if the following instruction is a store.
Implication: When this erratum occurs, incorrect information may exist in DR6. This erratum will not
be observed under normal usage of the MOV SS,r/m or POP SS instructions (i.e.,
following them with an instruction that writes [e/r]SP). When debugging or when
developing debuggers, this behavior should be noted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU40. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also
Result in a System Hang
Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in
another machine check bank (IA32_MCi_STATUS).
Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang
and an Internal Timer Error to be logged.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU41. IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
Problem: The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H
after reset; the correct value should be 0H.
Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset
(EN_FIXED_CTR{0, 1, 2} may be enabled).
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU42. Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Problem: Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication: Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
31
Specification Update
AAU43. Sleeping Cores May Not be Woken Up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
Problem: If software sends a logical cluster broadcast IPI using a destination shorthand of 00B
(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt
Command Register to all ones while not using all 1s in the mask portion of the
Destination Field, target cores in a sleep state that are identified by the mask portion of
the Destination Field may not be woken up. This erratum does not occur if the
destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).
Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle
the broadcast IPI. Intel has not observed this erratum with any commercially-available
software.
Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU44. Faulting Executions of FXRSTOR May Update State Inconsistently
Problem: The state updated by a faulting FXRSTOR instruction may vary from one execution to
another.
Implication: Software that relies on x87 state or SSE state following a faulting execution of
FXRSTOR may behave inconsistently.
Workaround: Software handling a fault on an execution of FXRSTOR can compensate for execution
variability by correcting the cause of the fault and executing FXRSTOR again.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU45. Performance Monitor Event EPT.EPDPE_MISS May be Counted While
EPT is Disable
Problem: Performance monitor event EPT.EPDPE_MISS (Event: 4FH, Umask: 08H) is used to
count Page Directory Pointer table misses while EPT (extended page tables) is enabled.
Due to this erratum, the processor will count Page Directory Pointer table misses
regardless of whether EPT is enabled or not.
Implication: Due to this erratum, performance monitor event EPT.EPDPE_MISS may report counts
higher than expected.
Workaround: Software should ensure this event is only enabled while in EPT mode.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU46. Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem: The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication: If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel® Architecture
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially-available software or
system.
Workaround: Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status: For the steppings affected, see the Summary Tables of Changes.
32
Specification Update
AAU47. Performance Monitor Counters May Count Incorrectly
Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H - C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround: Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished
by first disabling, saving valid events and clearing from the select registers, then
programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the
IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and
restoring previous programming if necessary. Each performance counter, IA32_PMCx,
must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of
the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits
[3:0]. All three values must be written to either the same or different
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status: For the steppings affected, see the Summary Tables of Changes.
AAU48. Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
Problem: When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0
event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is
counted. The following two selections do not provide accurate counts when counting NT
(Non-Temporal) Stores:
• OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
• OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have
been.
Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
33
Specification Update
AAU49. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
Problem: This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPTinduced
VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag
values that the EFLAGS register would have held had the instruction completed without
fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if
its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or
an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not
identified software that is affected by this erratum. This erratum will have no further
effects once the original instruction is restarted because the instruction will produce the
same results as if it had initially completed without fault or VM exit.
Workaround: If the handler of the affected events inspects the arithmetic portion of the saved
EFLAGS value, then system software should perform a synchronized paging structure
modification and TLB invalidation.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU50. Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
Problem: When back-to-back uncorrected machine check errors occur that would both be logged
in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16])
field may reflect the status of the most recent error and not the first error. The rest of
the IA32_MC3_STATUS MSR contains the information from the first error.
Implication: Software should not rely on the value of IA32_MC3_STATUS.MSCOD if
IA32_MC3_STATUS.OVER (bit [62]) is set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU51. Corrected Errors With a Yellow Error Indication May be Overwritten by
Other Corrected Errors
Problem: A corrected cache hierarchy data or tag error that is reported with
IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of 000x_0001_xxxx_xx01 (where
x stands for zero or one) and a yellow threshold-based error status indication (bits
[54:53] equal to 10B) may be overwritten by a corrected error with a no tracking
indication (00B) or green indication (01B).
Implication: Corrected errors with a yellow threshold-based error status indication may be
overwritten by a corrected error without a yellow indication.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
34
Specification Update
AAU52. Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem: The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication: The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU53. Rapid Core C3/C6 Transitions May Cause Unpredictable System
Behavior
Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions
in a system with Intel® Hyper-Threading Technology enabled may cause a machine
check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable
system behavior.
Implication: This erratum may cause a machine check error, system hang or unpredictable system
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU54. APIC Timer CCR May Report 0 in Periodic Mode
Problem: In periodic mode the APIC timer CCR (current-count register) is supposed to be
automatically reloaded from the initial-count register when the count reaches 0,
consequently software would never be able to observe a value of 0. Due to this
erratum, software may read 0 from the CCR when the timer has counted down and is in
the process of re-arming.
Implication: Due to this erratum, an unexpected value of 0 may be read from the APIC timer CCR
when in periodic mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU55. Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem: The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication: The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
35
Specification Update
AAU56. A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication: Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround: Software should not set Bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
"1".
Status: For the steppings affected, see the Summary Tables of Changes.
AAU57. BIST Results May be Additionally Reported After a GETSEC[WAKEUP]
or INIT-SIPI Sequence
Problem: BIST results should only be reported in EAX the first time a logical processor wakes up
from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally
reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep
state using the GETSEC[WAKEUP] command.
Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero
value is expected. RLP's waking up for the SENTER sleep state using the
GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than
before going into the SENTER sleep state.
Workaround: If necessary software may save the value in EAX prior to launching into the secure
environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU58. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executed while Enhanced Intel
SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or
Thermal Monitor events occur, the pending #MF may be signaled before pending
interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are serviced.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
36
Specification Update
AAU59. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
Problem: If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a
VM exit with exit reason "NMI window" should occur before execution of any instruction
if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of
events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of
events by either MOV SS or STI, such a VM exit should occur after execution of one
instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed
by one additional instruction.
Implication: VMM software using "NMI-window exiting" for NMI virtualization should generally be
unaffected, as the erratum causes at most a one-instruction delay in the injection of a
virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on
deterministic delivery of the affected VM exits.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU60. The Memory Controller tTHROT_OPREF Timings May be Violated
During Self Refresh Entry
Problem: During self refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU61. VM Exits Due to EPT Violations Do Not Record Information About Pre-
IRET NMI Blocking
Problem: With certain settings of the VM-execution controls VM exits due to EPT violations set bit
12 of the exit qualification if the EPT violation was a result of an execution of the IRET
instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this
erratum, such VM exits will instead clear this bit.
Implication: Due to this erratum, a virtual-machine monitor that relies on the proper setting of bit
12 of the exit qualification may deliver NMIs to guest software prematurely.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU62. Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
Problem: When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication: Multiple counter overflow interrupts may be unexpectedly generated.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
37
Specification Update
AAU63. LBRs May Not be Initialized During Power-On Reset of the Processor
Problem: If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of poweron
reset.
Workaround: Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU64. LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST Transition, T-states, C1E, or Adaptive
Thermal Throttling
Problem: The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
EIST (Enhanced Intel® SpeedStep Technology) transition, T-states, C1E (C1
Enhanced), or Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after an EIST transition, T-states, C1E, or
Adaptive Thermal Throttling.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU65. VMX-Preemption Timer Does Not Count Down at the Rate Specified
Problem: The VMX-preemption timer should count down by 1 every time a specific bit in the TSC
(Time Stamp Counter) changes. (This specific bit is indicated by IA32_VMX_MISC bits
[4:0] (0x485h) and has a value of 5 on the affected processors.) Due to this erratum,
the VMX-preemption timer may instead count down at a different rate and may do so
only intermittently.
Implication: The VMX-preemption timer may cause VM exits at a rate different from that expected
by software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
38
Specification Update
AAU66. Multiple Performance Monitor Interrupts are Possible on Overflow of
Fixed Counter 0
Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs.
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and
counter are configured as follows:
• Intel® Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = ‘1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = ‘1)
Implication: When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H) bit
[12].
Status: For the steppings affected, see the Summary Tables of Changes.
AAU67. VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
Problem: When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit
operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to
this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).
Implication: Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction information
field to determine the operand size of the instruction causing the VM exit.
Workaround: Virtual Machine Monitor software may decode the instruction to determine operand
size.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU68. Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Problem: Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA
should only increment the count when a load is blocked by a store. Due to this erratum,
the count will be incremented whenever a load hits a store, whether it is blocked or can
forward. In addition this event does not count for specific threads correctly.
Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events
STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence
of loads blocked by stores than have actually occurred. If Intel Hyper-Threading
Technology is enabled, the counts of loads blocked by stores may be unpredictable and
they could be higher or lower than the correct count.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
39
Specification Update
AAU69. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS
buffer. The information in the PEBS record represents the state of the next instruction
to be executed following the counter overflow. Due to this erratum, if the counter
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record being
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU70. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts
transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if
only a small number of MMX instructions (including EMMS) are executed immediately
after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU71. INVLPG Following INVEPT or INVVPID May Fail to Flush All
Translations for a Large Page
Problem: This erratum applies if the address of the memory operand of an INVEPT or INVVPID
instruction resides on a page larger than 4KBytes and either (1) that page includes the
low 1 MBytes of physical memory; or (2) the physical address of the memory operand
matches an MTRR that covers less than 4 MBytes. A subsequent execution of INVLPG
that targets the large page and that occurs before the next VM-entry instruction may
fail to flush all TLB entries for the page. Such entries may persist in the TLB until the
next VM-entry instruction.
Implication: Accesses to the large page between INVLPG and the next VM-entry instruction may
incorrectly use translations that are inconsistent with the in-memory page tables.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
40
Specification Update
AAU72. Logical Processor May Use Incorrect VPID after VM Entry That Returns
From SMM
Problem: A logical processor in VMX root operation should use VPID 0000H. Due to this erratum,
a logical processor may instead use VPID 1FB3H if VMX root operation was entered
using a VM entry that returns from SMM.
Implication: After a VM entry that sets the "enable VPID" VM-execution control and that establishes
VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in
VMX root operation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU73. The Memory Controller May Hang Due to Uncorrectable ECC Errors or
Parity Errors Occurring on Both Channels in Mirror Channel Mode
Problem: If an uncorrectable ECC or parity error occurs on the mirrored channel before an
uncorrectable ECC or parity error on the other channel can be resolved, the Memory
Controller may hang without an uncorrectable ECC or parity error being logged.
Implication: The processor may hang and not report the error when uncorrectable ECC or parity
errors occur in close proximity on both channels in a mirrored channel pair. No
uncorrectable ECC or parity error will be logged in the machine check banks.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU74. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost
Technology Core Ratio Multipliers for Non-Existent Core
Configurations
Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU75. Internal Parity Error May Be Incorrectly Signaled during C6 Exit
Problem: In a complex set of internal conditions an internal parity error may occur during a Core
C6 exit.
Implication: Due to this erratum, an uncorrected error may be reported and a machine check
exception may be triggered.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
41
Specification Update
AAU76. PMIs during Core C6 Transitions May Cause the System to Hang
Problem: If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core enters C6, then this may cause
the system to hang.
Implication: Due to this erratum, the processor may hang when a PMI coincides with core C6 entry.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU77. 2MB Page Split Lock Accesses Combined With Complex Internal
Events May Cause Unpredictable System Behavior
Problem: A 2MB Page Split Lock (a locked access that spans two 2MB large pages) coincident
with additional requests that have particular address relationships in combination with
a timing sensitive sequence of complex internal conditions may cause unpredictable
system behavior.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU78. If the APIC timer Divide Configuration Register (Offset 03E0H) is
written at the same time that the APIC timer Current Count Register
(Offset 0390H) reads 1H, it is possible that the APIC timer will deliver
two interrupts.
Problem: If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible
that the APIC timer will deliver two interrupts.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer
event.
Workaround: Software should reprogram the Divide Configuration Register only when the APIC timer
interrupt is disarmed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU79. TXT.PUBLIC.KEY is Not Reliable
Problem: On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the
TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to FED3_041FH) is not
reliable.
Implication: Due to this erratum, the TXT.PUBLIC.KEY value should not be relied on or used for
retrieving the hash of the TXT public key for the platform.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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Specification Update
AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides
With Interrupt Acknowledge Cycle From the Preceding Interrupt
Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External
Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External
Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B
Mode External Interrupt request. This occurs when both the new External Interrupt and
Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the
same time.
Implication: to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will
subsequently be ignored.
Workaround: Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU82. The APIC Timer Current Count Register May Prematurely Read 0x0
While the Timer is Still Running
Problem: The APIC Timer Current Counter Register may prematurely read 0x00000000 while the
timer is still running. This problem occurs when a core frequency or C-state transition
occurs while the APIC timer countdown is in progress.
Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer
countdown is complete when it is actually still running. This erratum does not affect the
delivery of the timer interrupt.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU83. Secondary PCIe Port May Not Train After A Warm Reset
Problem: In a dual PCIe port configuration, the secondary PCIe port may not train after a warm
reset.
Implication: The second PCIe port and therefore any device connected to the PCIe bus instantiated
by that PCIe port may not be functional after a warm reset. Intel has not observed this
erratum with any commercially available system.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
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Specification Update
AAU84. The PECI Bus May Be Tri-stated after System Reset
Problem: During power-up, the processor may improperly assert the PECI (Platform Environment
Control Interface) pin. This condition is cleared as soon as Bus Clock starts toggling.
However, if the PECI host (also referred to as the master or originator) incorrectly
determines this asserted state as another PECI host initiating a transaction, it may
release control of the bus resulting in a permanent tri-state condition.
Implication: Due to this erratum, the PECI host may incorrectly determine that it is not the bus
master and consequently PECI commands initiated by the PECI software layer may
receive incorrect/invalid responses.
Workaround: To workaround this erratum the PECI host should pull the PECI bus low to initiate a
PECI transaction.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU85. The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU86. Processor Hangs on Package C6 State Exit
Problem: An internal timing condition in the processor power management logic will result in
processor hangs upon a Package C6 state exit.
Implication: Due to this erratum, the processor will hang during Package C6 state exit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU87. A Synchronous SMI May be Delayed
Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI
generating I/O Write instruction and should be handled prior to the next instruction
executing. Due to this erratum, the processor may not observe the synchronous SMI
prior to execution of the next instruction.
Implication: Due to this erratum, instructions after the I/O Write instruction, which triggered the
SMI, may be allowed to execute before the SMI handler. Delayed delivery of the SMI
may make it difficult for an SMI Handler to determine the source of the SMI. Software
that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not
function as expected.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
44
Specification Update
AAU88. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses
are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU89. PCI Express x16 Port Links May Fail to Dynamically Switch From
5.0GT/s to 2.5GT/s
Problem: If an endpoint device initiates a PCI Express speed change from 5.0 GT/s to 2.5 GT/s,
the link may incorrectly go into Recovery.Idle rather than the expected Recovery.Speed
state. This may cause the link to lose sync, eventually resulting in a link down. The link
will recover and re-train to the L0 state, however any outstanding packets queued
during the speed change may be lost.
Implication: Due to this erratum, the link may lose sync resulting in link down with queued packet
being lost. No known failures have been observed on systems using production PCI
Express graphics cards. This erratum has only been observed in a synthetic test
environment.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU90. PCI Express Cards May Not Train to x16 Link Width
Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;
Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8,
even though the processor may actually be capable of supporting the full x16 width.
Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB
(Compliance Load Board) Cards used during PCI Express Compliance mode testing may
only train to x8 link width.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum
Status: For the steppings affected, see the Summary Tables of Changes.
AAU91. Unexpected Graphics VID Transition During Warm Reset May Cause
the System to Hang
Problem: During a warm reset to the processor, the graphics VID (Voltage ID) may transition to
an unexpected value that may cause the voltage regulator to shut off.
Implication: The processor may hang during integrated graphics initialization. Cold boots and
platforms using discrete graphics are not affected by this issue.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
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Status: For the steppings affected, see the Summary Tables of Changes.
Status:
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Specification Changes
The Specification Changes listed in this section apply to the following documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
There are no new Specification Changes in this Specification Update revision.
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Specification Clarifications
The Specification Clarifications listed in this section may apply to the following
documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
There are no new Specification Changes in this Specification Update revision.
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Specification Update
Documentation Changes
The Documentation Changes listed in this section apply to the following documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
All Documentation Changes will be incorporated into a future version of the appropriate
Processor documentation.
Note: Documentation changes for Intel® 64 and IA-32 Architecture Software
Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate
document, Intel® 64 and IA-32 Architecture Software Developer's Manual
Documentation Changes. Follow the link below to become familiar with this file.
http://developer.intel.com/products/processor/manuals/index.htm
AAU1. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet, Volume 2 to add
PEG_TC—PCI Express Completion Timeout Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2 will be updated to include the PEG_TC—PCI
Express Completion Timeout Register in Section 2.11.7 as shown in the table below in
red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet - Volume 2
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2.11.7 PEG_TC—PCI Express Completion Timeout Register
This register reports PCI Express configuration control of PCI Express Completion
Timeout related parameters that are not required by the PCI Express spec.
AAU2. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet, Volume 2 to add
PEG_TC—PCI Express Completion Timeout to add SSKPD—Sticky
Scratchpad Data Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2 will be updated to include the SSKPD—Sticky
Scratchpad Data Register in Section 2.8.56 as shown in the table below in red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2
B/D/F/Type: 0/1/0/MMR
Address Offset: 204h
Reset Value: 0000_0C00h
Access: RW
Bit Attr Reset
Value Description
31:12 RW 0000_0h Reserved: (RSVD).
11:12 RW 11b
PCI Express Completion Timeout (PEG_TC)
Determines the number of milliseconds the Transaction Layer will wait to
receive an expected completion. To avoid hang conditions, the Transaction
Layer will generate a dummy completion to the requestor if it does not
receive the completion within this time period.
00: Disable
01: Reserved
10: Reserved
11: 48 ms - for normal operation(default)
9:0 RW 0_0000_0
000b
Reserved: (RSVD).
50
Specification Update
2.8.56 SSKPD—Sticky Scratchpad Data Register
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
AAU3. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet - Volume 2 to add
MCSAMPML—Memory Configuration, System Address Map and Preallocated
Memory Lock Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2will be updated to include the
MCSAMPML—Memory Configuration, System Address Map and Pre-allocated Memory
Lock Register in Section 2.7.28 as shown in the table below in red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet - Volume 2
2.7.28 MCSAMPML—Memory Configuration, System Address Map
and Pre-allocated Memory Lock Register
B/D/F/Type: 0/0/0/PCI
Address Offset: F4h
Reset Value: 00h
Access:
Bit Attr Reset
Value Description
7:5 RW-O 000b Reserved(RSDV)
4 RW-L 0 Reserved(RSDV)
3 RW-L-K 0
Lock Mode (LOCKMODE)
LOCKMODE and ME_SM_LOCK (bit 0) must always be programmed to the
same value. See bit 0 for description details.
0 = Registers are not locked
1 = Registers are locked.
2 RW-L 0 Reserved(RSDV)
1 RO 0 Reserved(RSDV)
0 RW-L-K 0
ME Stolen Memory Lock (ME_SM_LOCK)
When ME_SM_LOCK is set to 1 then all registers related to MCH configuration
become read only. BIOS will initialize config bits related to MCH configuration
and then use ME_SM_lock to "lock down" the MCH configuration in the future
so that no application software (or BIOS itself) can violate the integrity of
DRAM - including ME stolen memory space.
If BIOS writes this bit to '1` then bit 3 "LOCKMODE" bit must also be written
to '1` to ensure proper register lockdown.
If BIOS writes this bit to '0` then bit 3 "LOCKMODE" bit must also be written
to '0`.
This bit and LOCKMODE bit 3 should never be programmed differently.
PCI device 0 and MCHBAR registers affected by this bit are detailed within
the descriptions of the affected registers.
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Reference Number: 322911-003
Intel® Core™ i5-600, i3-500
Desktop Processor Series and
Intel® Pentium Processor G6950
Specification Update
March 2010
Revision -003
2
Specification Update
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host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/
technology/platform-technology/intel-amt/
Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology (Intel® Virtualization Technology
(Intel® VT-x) and Intel® Virtualization Technology for Directed I/O (Intel® VT-d)), a Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an
application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for
some uses. For more information, see http://www.intel.com/technology/security
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some
uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software
configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your
application vendor.
* Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology
performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system
delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost
Intel® Hyper-threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset,
BIOS, and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details
on which processors support HT Technology, see http://www.intel.com/info/hyperthreading.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications
enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor
for more information.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-
4725 or by visiting Intel's website at http://www.intel.com.
Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Intel Corporation. All Rights Reserved.
Contents
3
Specification Update
Contents
Revision History...............................................................................................................5
Preface ..............................................................................................................................6
Summary Tables of Changes..........................................................................................8
Identification Information ..............................................................................................16
Errata ...............................................................................................................................18
Specification Changes...................................................................................................43
Specification Clarifications ...........................................................................................44
Documentation Changes...............................................................................................45
§
Contents
4
Specification Update
5
Specification Update
Revision History
Revision Description Date
-001 Initial Release January 2010
-002
Added Errata AAU85-AAU87.
Corrected Extended Model and Model Number register values in Component Identification
table.
February 2010
-003
Added Errata AAU88-AAU91.
Added Documentation Changes AAU1-AAU3.
March 2010
6
Specification Update
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Related Documents
Document Title Document
Number
Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 1 322909-001
Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2 322910-001
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID Instruction http://www.intel.com/
design/processor/
applnots/241618.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel® 64 and IA-32 Intel Architecture Optimization Reference
Manual
http://www.intel.com/
products/processor/
manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes
http://www.intel.com/
design/processor/
specupdt/252046.htm
ACPI Specifications www.acpi.info
7
Specification Update
Nomenclature
Errata are design defects or errors. These may cause the processor behavior to
deviate from published specifications. Hardware and software designed to be used with
any given stepping must assume that all errata documented for that stepping are
present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics such as, core speed, L2 cache size,
package type, etc. as described in the processor identification information table. Read
all notes associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
8
Specification Update
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of a table row indicates this erratum is either new or modified from
the previous version of the document.
9
Specification Update
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading technology on 90-
nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache
versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel® processor
A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme
Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process
AF = Intel® Xeon® processor LV
AG = Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000
and E4000 sequence
10
Specification Update
AJ = Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad
processor Q6000 sequence
AL = Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Intel® Xeon® processor 3200 series
AP = Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AU = Intel® Celeron® dual-core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000
series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Intel® Xeon® processor 5400 series
AY = Intel® Xeon® processor 5200 series
AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process
AAA= Intel® Xeon® processor 3300 series
AAB= Intel® Xeon® E3110 processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme processor QX9775
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ processor 300 series
AAI = Intel® Xeon® processor 7400 series
AAJ = Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900
desktop processor series
AAK= Intel® Xeon® processor 5500 series
AAL = Intel® Pentium® dual-core processor E5000 series
AAN = Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950
AAO = Intel® Xeon® processor 3400 series
AAP = Intel® Core™ i7-900 mobile processor Extreme Edition series, Intel Core i7-800 and i7-700
mobile processor series
AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 mobile processor series
AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor
G6950
11
Specification Update
Errata (Sheet 1 of 4)
Number
Steppings
Status ERRATA
C-2
AAU1 X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAU2 X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations
AAU3 X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack
AAU4 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAU5 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AAU6 X No Fix MOV To/From Debug Registers Causes Debug Exception
AAU7 X No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
AAU8 X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
AAU9 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
AAU10 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAU11 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AAU12 X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
Preempted
AAU13 X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
AAU14 X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs
in 64-bit Mode
AAU15 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
Error
AAU16 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints
AAU17 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAU18 X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
AAU19 X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy
Counter may be Incorrect
AAU20 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAU21 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAU22 X No Fix #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not
Provide Correct Exception Error Code
AAU23 X No Fix Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is
Set on a #GP Instruction
AAU24 X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point
Exception
AAU25 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1
AAU26 X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not
Work
12
Specification Update
AAU27 X No Fix? Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in
Stuck Core Operating Ratio
AAU28 X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an
Unexpected Interrupt
AAU29 X No Fix xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in
Periodic Mode
AAU30 X No Fix Reported Memory Type May Not Be Used to Access the VMCS and Referenced
Data Structures
AAU31 X No Fix Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
Ordering Violations
AAU32 X No Fix Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write
Major Mode Enabled
AAU33 X Plan Fix Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted
RIP onto the Stack
AAU34 X No Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is
Received while All Cores in C6
AAU35 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
AAU36 X No Fix EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt
Service Routine
AAU37 X No Fix FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
AAU38 X No Fix APIC Error “Received Illegal Vector” May be Lost
AAU39 X No Fix DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/
m or POP SS is a Store
AAU40 X No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a
System Hang
AAU41 X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
AAU42 X No Fix Performance Monitor Counter INST_RETIRED.STORES May Count Higher than
Expected
AAU43 X No Fix Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using
Destination Field Instead of Shorthand
AAU44 X No Fix Faulting Executions of FXRSTOR May Update State Inconsistently
AAU45 X No Fix Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is
Disable
AAU46 X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
AAU47 X No Fix Performance Monitor Counters May Count Incorrectly
AAU48 X No Fix Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores
to Local DRAM Correctly
AAU49 X No Fix EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
Translation Change
AAU50 X No Fix Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
AAU51 X No Fix Corrected Errors With a Yellow Error Indication May be Overwritten by Other
Corrected Errors
Errata (Sheet 2 of 4)
Number
Steppings
Status ERRATA
C-2
13
Specification Update
AAU52 X No Fix Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST
May Overcount
AAU53 X No Fix Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior
AAU54 X No Fix APIC Timer CCR May Report 0 in Periodic Mode
AAU55 X No Fix Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May
Count Inaccurately
AAU56 X No Fix A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or
PDPTE
AAU57 X No Fix BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-SIPI
Sequence
AAU58 X No Fix Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
AAU59 X No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
AAU60 X No Fix The Memory Controller tTHROT_OPREF Timings May be Violated During Self
Refresh Entry
AAU61 X No Fix VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI
Blocking
AAU62 X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
AAU63 X No Fix LBRs May Not be Initialized During Power-On Reset of the Processor
AAU64 X No Fix LBR, BTM or BTS Records May have Incorrect Branch From Information After an
EIST Transition, T-states, C1E, or Adaptive Thermal Throttling
AAU65 X No Fix VMX-Preemption Timer Does Not Count Down at the Rate Specified
AAU66 X No Fix Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter
0
AAU67 X No Fix VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size
AAU68 X No Fix Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
AAU69 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI
AAU70 X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
Transitions
AAU71 X No Fix INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a
Large Page
AAU72 X No Fix Logical Processor May Use Incorrect VPID after VM Entry That Returns From SMM
AAU73 X No Fix The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors
Occurring on Both Channels in Mirror Channel Mode
AAU74 X No Fix MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core
Ratio Multipliers for Non-Existent Core Configurations
AAU75 X Plan Fix Internal Parity Error May Be Incorrectly Signaled during C6 Exit
AAU76 X No Fix PMIs during Core C6 Transitions May Cause the System to Hang
AAU77 X No Fix 2MB Page Split Lock Accesses Combined With Complex Internal Events May
Cause Unpredictable System Behavior
Errata (Sheet 3 of 4)
Number
Steppings
Status ERRATA
C-2
14
Specification Update
AAU78 X No Fix
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is
possible that the APIC timer will deliver two interrupts.
AAU79 X Plan Fix TXT.PUBLIC.KEY is Not Reliable
AAU80 X Plan Fix 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt
Acknowledge Cycle From the Preceding Interrupt
AAU82 X No Fix The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer
is Still Running
AAU83 X No Fix Secondary PCIe Port May Not Train After A Warm Reset
AAU84 X No Fix The PECI Bus May Be Tri-stated after System Reset
AAU85 X No Fix The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
AAU86 X No Fix Processor Hangs on Package C6 State Exit
AAU87 X No Fix A Synchronous SMI May be Delayed
AAU88 X No Fix FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
AAU89 X Plan Fix PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/
s
AAU90 X No Fix PCI Express Cards May Not Train to x16 Link Width
AAU91 X No Fix Unexpected Graphics VID Transition During Warm Reset May Cause the System to
Hang
Specification Changes
Number SPECIFICATION CHANGES
None for this revision of this specification update.
Specification Clarifications
Number SPECIFICATION CLARIFICATIONS
None for this revision of this specification update.
Errata (Sheet 4 of 4)
Number
Steppings
Status ERRATA
C-2
15
Specification Update
Documentation Changes
Number DOCUMENTATION CHANGES
AAU1
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add PEG_TC—PCI Express Completion
Timeout RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2 to add PEG_TC—PCI Express Completion Timeout Register
AAU2
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add SSKPD—Sticky Scratchpad Data
RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950
Datasheet, Volume 2 to add PEG_TC—PCI Express Completion Timeout to add SSKPD—Sticky Scratchpad Data
Register
AAU3
Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 and Intel®
Xeon® Processor L3406 External Design Specification – Volume 2 to add MCSAMPML—Memory Configuration,
System Address Map and Pre-allocated Memory Lock RegisterUpdate to Intel® Core™ i5-600, i3-500 Desktop
Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volume 2 to add MCSAMPML—Memory
Configuration, System Address Map and Pre-allocated Memory Lock Register
16
Specification Update
Identification Information
Component Identification using Programming Interface
The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 stepping can be identified by the following register contents:
Note:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],
to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,
or Intel® Core™ processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are
used to identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM
processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor
system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of
the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX
register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the
Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor
stepping ID number in the CPUID information.
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended
Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID
value in the EAX register. Note that the EDX processor signature value after reset is
equivalent to the processor signature output value in the EAX register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 can be identified by the following register contents:
Notes:
1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI
function 0 configuration space.
2. The Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in
the PCI function 0 configuration space.
3. The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI
function 0 configuration space.
Reserved Extended
Family1
Extended
Model2 Reserved Processor
Type3
Family
Code4
Model
Number5
Stepping
ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0010b 00b 0110 0101b xxxxb
Stepping Vendor ID1 Device ID2 Revision ID3
C-2 8086h 0040h 12h
17
Specification Update
Component Marking Information
The processor stepping can be identified by the following component markings.
Notes:
1. This processor has TDP of 73 W.
2. This column indicates maximum Intel® Turbo Boost Technology frequency (GHz) for 2 or 1 cores active
respectively.
3. Intel® Hyper-Threading Technology enabled.
4. Intel® Trusted Execution Technology (Intel® TXT) enabled.
5. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.
6. Intel® Virtualization Technology for Directed I/O (Intel® VT-d) enabled.
7. Intel® AES-NI enabled.
8. Intel SSE4.1 and SSE4.2 enabled.
9. This processor has TDP of 87 W.
10. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example,
core frequency of 3.4666, repeating 6, is reported as @3.47 in brand string. Core frequency of 3.3333,
is reported as @3.33 in brand string.)
Figure 1. Processor Production Top-side Markings (Example)
Table 1. Processor Identification
S-Spec
Number
Processor
Number Stepping Processor
Signature
Core Frequency
(GHz) /
DDR3 (MHz) /
Integrated
Graphics
Frequency
Max Intel®
Turbo Boost
Technology
Frequency
(GHz)2
Shared
L3 Cache
Size (MB)
Notes
LBLT i5-670 C-2 20652h 3.46 / 1333 / 733
2 core: 3.60
1 core: 3.73
4
1, 3, 4, 5, 6,
7, 8, 11
LBNE i5-661 C-2 20652h 3.33 / 1333 / 900
2 core: 3.46
1 core: 3.60
4
3, 5, 7, 8, 9,
11
LBLV i5-660 C-2 20652h 3.33 / 1333 / 733
2 core: 3.46
1 core: 3.60
4
1, 3, 4, 5, 6,
7, 8, 11
LBLK i5-650 C-2 20652h 3.20 / 1333 / 733
2 core: 3.33
1 core: 3.46
4
1, 3, 4, 5, 6,
7, 8, 11
LBMQ i3-540 C-2 20652h 3.06 / 1333 / 733 N/A 4
1, 3, 5, 8,
11
LBLR i3-530 C-2 20652h 2.93 / 1333 / 733 N/A 4
1, 3, 5, 8,
11
LBMS G6950 C-2 20652h 2.80 / 1066 / 533 N/A 3 1, 5, 11
LOT NO S/N
INTEL ©'08 PROC#
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18
Specification Update
Errata
AAU1. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the Software Developers Manual section "Outof-
Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family
Processors" the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.
19
Specification Update
AAU3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before
Higher Priority Interrupts/Exceptions and May Push the Wrong
Address onto the Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a noncanonical
address, the address pushed onto the stack for this #GP fault may not match
the non-canonical address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commerciallyavailable
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU4. Performance Monitor SSE Retired Instructions May Return Incorrect
Values
Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU5. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: If any of the below circumstances occur, it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
• If an instruction that performs a memory load causes a code segment limit
violation.
• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Topof-
Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, or from the
restart and subsequent re-execution of that instruction by the exception handler. If the
target of the load is to uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the repetition of the sideeffect.
Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register
operands may issue a memory load before getting the DNA exception.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
20
Specification Update
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU6. MOV To/From Debug Registers Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU8. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also be
incorrect.
Problem: Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
21
Specification Update
AAU9. Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem: In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
• #DB is signaled before the pending higher priority #MF (Interrupt 16)
• #DB is generated twice on the same instruction
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU10. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e., residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Refer to "Procedure Calls For Block-Structured Languages" in IA-32 Intel®
Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on
the usage of the ENTER instructions. This erratum is not expected to occur in Ring 3.
Faults are usually processed in Ring 0 and stack switch occurs when transferring to
Ring 0. Intel has not observed this erratum on any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU11. IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if
alignment checks are disabled at the start of the IRET. This erratum can only be
observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status: For the steppings affected, see the Summary Tables of Changes.
22
Specification Update
AAU12. General Protection Fault (#GP) for Instructions Greater than 15 Bytes
May be Preempted
Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a
#GP is signaled when the instruction is decoded. Under some circumstances, the #GP
fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)).
However, if the preempting lower priority faults are resolved by the operating system
and the instruction retried, a #GP fault will occur.
Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.
Instructions of greater than 15 bytes in length can only occur if redundant prefixes are
placed before the instruction.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU13. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that
occur above the 4-G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP
fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the
4-G limit (0ffffffffh).
Status: For the steppings affected, see the Summary Tables of Changes.
AAU14. LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,
during a specific boundary condition where the exception/interrupt occurs right after
the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)
in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63
to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which
report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/
interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU15. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the
Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error
code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status
register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate
indication of multiple occurrences of DTLB errors. There is no other impact to normal
processor functionality.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
23
Specification Update
AAU16. Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
Problem: When a debug exception is signaled on a load that crosses cache lines with data
forwarded from a store and whose corresponding breakpoint enable flags are disabled
(DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.
Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the
corresponding breakpoint enable flag in DR7 is disabled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU17. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in
Hang
Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local
xAPIC's address space, the processor will hang.
Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space
must be uncached. The MONITOR instruction only functions correctly if the specified
linear address range is of the type write-back. CLFLUSH flushes data from the cache.
Intel has not observed this erratum with any commercially-available software.
Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU18. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first FAR JMP, the subsequent RSM (Resume from System
Management Mode) may cause the lower two bits of CS segment register to be
corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software
Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the FAR JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU19. Performance Monitoring Events for Read Miss to Level 3 Cache Fill
Occupancy Counter may be Incorrect
Problem: Whenever an Level 3 cache fill conflicts with another request's address, the miss to fill
occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H), will provide erroneous
results.
Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS event may count a value
higher than expected. The extent to which the value is higher than expected is
determined by the frequency of the L3 address conflict.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
24
Specification Update
AAU20. A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware
as Armed
Problem: A processor write to the address range armed by the MONITOR instruction may not
immediately trigger the monitoring hardware. Consequently, a VM exit on a later
MWAIT may incorrectly report the monitoring hardware as armed, when it should be
reported as unarmed due to the write occurring prior to the MWAIT.
Implication: If a write to the range armed by the MONITOR instruction occurs between the
MONITOR and the MWAIT, the MWAIT instruction may start executing before the
monitoring hardware is triggered. If the MWAIT instruction causes a VM exit, this could
cause its exit qualification to incorrectly report 0x1. In the recommended usage model
for MONITOR/MWAIT, there is no write to the range armed by the MONITOR instruction
between the MONITOR and the MWAIT.
Workaround: Software should never write to the address range armed by the MONITOR instruction
between the MONITOR and the subsequent MWAIT.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU21. Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
Problem: The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts
instructions that load new values into segment registers. The value of the count may be
inaccurate.
Implication: The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or
lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU22. #GP on Segment Selector Descriptor that Straddles Canonical
Boundary May Not Provide Correct Exception Error Code
Problem: During a #GP (General Protection Exception), the processor pushes an error code on to
the exception handler’s stack. If the segment selector descriptor straddles the
canonical boundary, the error code pushed onto the stack may be incorrect.
Status: An incorrect error code may be pushed onto the stack. Intel has not observed this
erratum with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU23. Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
Problem: While coming out of cold reset or exiting from C6, if the processor encounters an
instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is
enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly
logged resulting in an MCE (Machine Check Exception).
Implication: When this erratum occurs, an MCE may be incorrectly signaled.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
25
Specification Update
AAU24. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the sequential
execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an
invalid stack during interrupt handling. However, an enabled debug breakpoint or single
step trap may be taken after MOV SS/POP SS if this instruction is followed by an
instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP
instruction. This results in a debug exception being signaled on an unexpected
instruction boundary since the MOV SS/POP SS and the following instruction should be
executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP,
[r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any
exception. Intel has not observed this erratum with any commercially-available
software or system.
Workaround: As recommended in the IA32 Intel® Architecture Software Developer’s Manual, the use
of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since
the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of
debug tools should be aware of the potential incorrect debug event signaling created by
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU25. IA32_MPERF Counter Stops Counting During On-Demand TM1
Problem: According to the Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to
IA32_APERF (MSR E8H) should reflect actual performance while TM1 or on-demand
throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while TM1
or on-demand throttling is activated, and the ratio of the two will indicate higher
processor performance than actual.
Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state
(performance state) management algorithms under the conditions described above. It
is possible for the Operating System to observe higher processor utilization than actual,
which could lead the OS into raising the P-state. During TM1 activation, the OS P-state
request is irrelevant and while on-demand throttling is enabled, it is expected that the
OS will not be changing the P-state. This erratum should result in no practical
implication to software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU26. Synchronous Reset of IA32_APERF/IA32_MPERF Counters on
Overflow Does Not Work
Problem: When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously
reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both
MSRs increment and overflow independently.
Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
26
Specification Update
AAU27. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,
May Result in Stuck Core Operating Ratio
Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then
Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a
subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the
maximum core P-state. The ceiling is based on the core frequency at the time of
Thermal Monitor disable. This condition will only correct itself once the processor
reaches its TCC activation temperature again.
Implication: Since Intel requires that Thermal Monitor be enabled in order to be operating within
specification, this erratum should never be seen during normal operation.
Workaround: Software should not disable Thermal Monitor during processor operation.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU28. Writing the Local Vector Table (LVT) when an Interrupt is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service
Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an
End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and
mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU29. xAPIC Timer May Decrement Too Quickly Following an Automatic
Reload While in Periodic Mode
Problem: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Implication: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic
mode, the xAPIC Timer may slip in its synchronization with the external clock. The
xAPIC timer may be shortened by up to one xAPIC timer tick.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
27
Specification Update
AAU30. Reported Memory Type May Not Be Used to Access the VMCS and
Referenced Data Structures
Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor
uses to access the VMCS and data structures referenced by pointers in the VMCS. Due
to this erratum, a VMX access to the VMCS or referenced data structures will instead
use the memory type that the MTRRs (memory-type range registers) specify for the
physical address of the access.
Implication: Bits 53:50 of the IA32_VMX_BASIC MSR report that the WB (write-back) memory type
will be used but the processor may use a different memory type.
Workaround: Software should ensure that the VMCS and referenced data structures are located at
physical addresses that are mapped to WB memory type by the MTRRs.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU31. Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Problem: Under complex microarchitectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Implication: Memory ordering may be violated. Intel has not observed this erratum with any
commercially-available software.
Workaround: Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU32. Critical ISOCH Traffic May Cause Unpredictable System Behavior When
Write Major Mode Enabled
Problem: Under a specific set of conditions, critical ISOCH (isochronous) traffic may cause
unpredictable system behavior with write major mode enabled.
Implication: Due to this erratum unpredictable system behavior may occur.
Workaround: Write major mode must be disabled in the BIOS by writing the write major mode
threshold value to its maximum value of 1FH in ISOCHEXITTRESHOLD bits [19:15],
ISOCHENTRYTHRESHOLD bits [14:10], WMENTRYTHRESHOLD bits [9:5], and
WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0,1,2}_WAQ_PARAMS register.
Status: For the steppings affected, see the Summary Tables of Changes.
28
Specification Update
AAU33. Delivery of Certain Events Immediately Following a VM Exit May Push
a Corrupted RIP onto the Stack
Problem: If any of the following events is delivered immediately following a VM exit to 64-bit
mode from outside 64-bit mode, bits 63:32 of the RIP value pushed on the stack may
be cleared to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction fetch; or
• A general-protection exception (#GP) due to an attempt to decode an instruction
whose length is greater than 15 bytes.
Implication: Unexpected behavior may occur due to the incorrect value of the RIP on the stack.
Specifically, return from the event handler via IRET may encounter an unexpected page
fault or may begin fetching from an unexpected code address.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU34. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
Problem: If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1).
However, the pending interrupt event will not be cleared.
Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the
external interrupt. Intel has not observed this erratum with any commercially-available
software/system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU35. Two xAPIC Timer Event Interrupts May Unexpectedly Occur
Problem: If an xAPIC timer event is enabled and while counting down the current count reaches
1 at the same time that the processor thread begins a transition to a low power Cstate,
the xAPIC may generate two interrupts instead of the expected one when the
processor returns to C0.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer
event.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
29
Specification Update
AAU36. EOI Transaction May Not be Sent if Software Enters Core C6 During an
Interrupt Service Routine
Problem: If core C6 is entered after the start of an interrupt service routine but before a write to
the APIC EOI register, the core may not send an EOI transaction (if needed) and further
interrupts from the same priority level or lower may be blocked.
Implication: EOI transactions and interrupts may be blocked when core C6 is used during interrupt
service routines. Intel has not observed this erratum with any commercially-available
software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU37. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS
During SMM
Problem: In general, a PEBS record should be generated on the first count of the event after the
counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR
1D9H, bit [14]) prevents performance counters from counting during SMM (System
Management Mode). Due to this erratum, if
1. A performance counter overflowed before an SMI
2. A PEBS record has not yet been generated because another count of the event has
not occurred
3. The monitored event occurs during SMM
then a PEBS record will be saved after the next RSM instruction.
When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event
occurs outside of SMM.
Implication: A PEBS record may be saved after an RSM instruction due to the associated
performance counter detecting the monitored event during SMM; even when
FREEZE_WHILE_SMM is set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU38. APIC Error “Received Illegal Vector” May be Lost
Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error
Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error
is received on the same internal clock that the ESR is being written (as part of the
write-read ESR access flow). The corresponding error interrupt will also not be
generated for this case.
Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR
properly and may not generate an error interrupt.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
30
Specification Update
AAU39. DR6 May Contain Incorrect Information When the First Instruction
After a MOV SS,r/m or POP SS is a Store
Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused
by the previous instruction. However, the instruction following a MOV SS,r/m (MOV to
the stack segment selector) or POP SS (POP stack segment selector) instruction will not
clear the changes in DR6 because data breakpoints are not taken immediately after a
MOV SS,r/m or POP SS instruction. Due to this erratum, any DR6 changes caused by a
MOV SS,r/m or POP SS instruction may be cleared if the following instruction is a store.
Implication: When this erratum occurs, incorrect information may exist in DR6. This erratum will not
be observed under normal usage of the MOV SS,r/m or POP SS instructions (i.e.,
following them with an instruction that writes [e/r]SP). When debugging or when
developing debuggers, this behavior should be noted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU40. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also
Result in a System Hang
Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a
system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in
another machine check bank (IA32_MCi_STATUS).
Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang
and an Internal Timer Error to be logged.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU41. IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized
Problem: The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H
after reset; the correct value should be 0H.
Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset
(EN_FIXED_CTR{0, 1, 2} may be enabled).
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU42. Performance Monitor Counter INST_RETIRED.STORES May Count
Higher than Expected
Problem: Performance Monitoring counter INST_RETIRED.STORES (Event: C0H) is used to track
retired instructions which contain a store operation. Due to this erratum, the processor
may also count other types of instructions including WRMSR and MFENCE.
Implication: Performance Monitoring counter INST_RETIRED.STORES may report counts higher than
expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
31
Specification Update
AAU43. Sleeping Cores May Not be Woken Up on Logical Cluster Mode
Broadcast IPI Using Destination Field Instead of Shorthand
Problem: If software sends a logical cluster broadcast IPI using a destination shorthand of 00B
(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt
Command Register to all ones while not using all 1s in the mask portion of the
Destination Field, target cores in a sleep state that are identified by the mask portion of
the Destination Field may not be woken up. This erratum does not occur if the
destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).
Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle
the broadcast IPI. Intel has not observed this erratum with any commercially-available
software.
Workaround: Use destination shorthand of 10B or 11B to send broadcast IPIs.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU44. Faulting Executions of FXRSTOR May Update State Inconsistently
Problem: The state updated by a faulting FXRSTOR instruction may vary from one execution to
another.
Implication: Software that relies on x87 state or SSE state following a faulting execution of
FXRSTOR may behave inconsistently.
Workaround: Software handling a fault on an execution of FXRSTOR can compensate for execution
variability by correcting the cause of the fault and executing FXRSTOR again.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU45. Performance Monitor Event EPT.EPDPE_MISS May be Counted While
EPT is Disable
Problem: Performance monitor event EPT.EPDPE_MISS (Event: 4FH, Umask: 08H) is used to
count Page Directory Pointer table misses while EPT (extended page tables) is enabled.
Due to this erratum, the processor will count Page Directory Pointer table misses
regardless of whether EPT is enabled or not.
Implication: Due to this erratum, performance monitor event EPT.EPDPE_MISS may report counts
higher than expected.
Workaround: Software should ensure this event is only enabled while in EPT mode.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU46. Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem: The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication: If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the Intel 64 and IA-32 Intel® Architecture
Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.
Intel has not observed this erratum with any commercially-available software or
system.
Workaround: Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status: For the steppings affected, see the Summary Tables of Changes.
32
Specification Update
AAU47. Performance Monitor Counters May Count Incorrectly
Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H - C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround: Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished
by first disabling, saving valid events and clearing from the select registers, then
programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the
IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and
restoring previous programming if necessary. Each performance counter, IA32_PMCx,
must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of
the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits
[3:0]. All three values must be written to either the same or different
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status: For the steppings affected, see the Summary Tables of Changes.
AAU48. Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
Problem: When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0
event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is
counted. The following two selections do not provide accurate counts when counting NT
(Non-Temporal) Stores:
• OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
• OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have
been.
Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
33
Specification Update
AAU49. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
Problem: This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPTinduced
VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag
values that the EFLAGS register would have held had the instruction completed without
fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if
its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or
an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not
identified software that is affected by this erratum. This erratum will have no further
effects once the original instruction is restarted because the instruction will produce the
same results as if it had initially completed without fault or VM exit.
Workaround: If the handler of the affected events inspects the arithmetic portion of the saved
EFLAGS value, then system software should perform a synchronized paging structure
modification and TLB invalidation.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU50. Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
Problem: When back-to-back uncorrected machine check errors occur that would both be logged
in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16])
field may reflect the status of the most recent error and not the first error. The rest of
the IA32_MC3_STATUS MSR contains the information from the first error.
Implication: Software should not rely on the value of IA32_MC3_STATUS.MSCOD if
IA32_MC3_STATUS.OVER (bit [62]) is set.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU51. Corrected Errors With a Yellow Error Indication May be Overwritten by
Other Corrected Errors
Problem: A corrected cache hierarchy data or tag error that is reported with
IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of 000x_0001_xxxx_xx01 (where
x stands for zero or one) and a yellow threshold-based error status indication (bits
[54:53] equal to 10B) may be overwritten by a corrected error with a no tracking
indication (00B) or green indication (01B).
Implication: Corrected errors with a yellow threshold-based error status indication may be
overwritten by a corrected error without a yellow indication.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
34
Specification Update
AAU52. Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem: The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication: The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU53. Rapid Core C3/C6 Transitions May Cause Unpredictable System
Behavior
Problem: Under a complex set of internal conditions, cores rapidly performing C3/C6 transitions
in a system with Intel® Hyper-Threading Technology enabled may cause a machine
check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable
system behavior.
Implication: This erratum may cause a machine check error, system hang or unpredictable system
behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU54. APIC Timer CCR May Report 0 in Periodic Mode
Problem: In periodic mode the APIC timer CCR (current-count register) is supposed to be
automatically reloaded from the initial-count register when the count reaches 0,
consequently software would never be able to observe a value of 0. Due to this
erratum, software may read 0 from the CCR when the timer has counted down and is in
the process of re-arming.
Implication: Due to this erratum, an unexpected value of 0 may be read from the APIC timer CCR
when in periodic mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU55. Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem: The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
of load or store instructions retired. However, due to this erratum, they may
undercount.
Implication: The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect
a count lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
35
Specification Update
AAU56. A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due
to this erratum, PS of such an entry is ignored and no page fault will occur due to its
being set.
Implication: Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround: Software should not set Bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
"1".
Status: For the steppings affected, see the Summary Tables of Changes.
AAU57. BIST Results May be Additionally Reported After a GETSEC[WAKEUP]
or INIT-SIPI Sequence
Problem: BIST results should only be reported in EAX the first time a logical processor wakes up
from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally
reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep
state using the GETSEC[WAKEUP] command.
Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero
value is expected. RLP's waking up for the SENTER sleep state using the
GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than
before going into the SENTER sleep state.
Workaround: If necessary software may save the value in EAX prior to launching into the secure
environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU58. Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executed while Enhanced Intel
SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or
Thermal Monitor events occur, the pending #MF may be signaled before pending
interrupts are serviced.
Implication: Software may observe #MF being signaled before pending interrupts are serviced.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
36
Specification Update
AAU59. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
Problem: If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a
VM exit with exit reason "NMI window" should occur before execution of any instruction
if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of
events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of
events by either MOV SS or STI, such a VM exit should occur after execution of one
instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed
by one additional instruction.
Implication: VMM software using "NMI-window exiting" for NMI virtualization should generally be
unaffected, as the erratum causes at most a one-instruction delay in the injection of a
virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on
deterministic delivery of the affected VM exits.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU60. The Memory Controller tTHROT_OPREF Timings May be Violated
During Self Refresh Entry
Problem: During self refresh entry, the memory controller may issue more refreshes than
permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING
CSR).
Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near
self refresh entry are not critical, there is no measurable impact due to this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU61. VM Exits Due to EPT Violations Do Not Record Information About Pre-
IRET NMI Blocking
Problem: With certain settings of the VM-execution controls VM exits due to EPT violations set bit
12 of the exit qualification if the EPT violation was a result of an execution of the IRET
instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this
erratum, such VM exits will instead clear this bit.
Implication: Due to this erratum, a virtual-machine monitor that relies on the proper setting of bit
12 of the exit qualification may deliver NMIs to guest software prematurely.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU62. Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
Problem: When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication: Multiple counter overflow interrupts may be unexpectedly generated.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
37
Specification Update
AAU63. LBRs May Not be Initialized During Power-On Reset of the Processor
Problem: If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last
Branch Records) may not be properly initialized.
Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of poweron
reset.
Workaround: Ensure that the processor has completed its power-on reset cycle prior to initiating a
second reset.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU64. LBR, BTM or BTS Records May have Incorrect Branch From
Information After an EIST Transition, T-states, C1E, or Adaptive
Thermal Throttling
Problem: The "From" address associated with the LBR (Last Branch Record), BTM (Branch Trace
Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an
EIST (Enhanced Intel® SpeedStep Technology) transition, T-states, C1E (C1
Enhanced), or Adaptive Thermal Throttling.
Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch
"From" addresses for the first branch after an EIST transition, T-states, C1E, or
Adaptive Thermal Throttling.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU65. VMX-Preemption Timer Does Not Count Down at the Rate Specified
Problem: The VMX-preemption timer should count down by 1 every time a specific bit in the TSC
(Time Stamp Counter) changes. (This specific bit is indicated by IA32_VMX_MISC bits
[4:0] (0x485h) and has a value of 5 on the affected processors.) Due to this erratum,
the VMX-preemption timer may instead count down at a different rate and may do so
only intermittently.
Implication: The VMX-preemption timer may cause VM exits at a rate different from that expected
by software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
38
Specification Update
AAU66. Multiple Performance Monitor Interrupts are Possible on Overflow of
Fixed Counter 0
Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon
overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on
overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum
occurs.
This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and
counter are configured as follows:
• Intel® Hyper-Threading Technology is enabled
• IA32_FIXED_CTR0 local and global controls are enabled
• IA32_FIXED_CTR0 is set to count events only on its own thread
(IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0)
• PMIs are enabled on IA32_FIXED_CTR0 (IA32_FIXED_CTR_CTRL MSR bit [3] = ‘1)
• Freeze_on_PMI feature is enabled (IA32_DEBUGCTL MSR (1D9H) bit [12] = ‘1)
Implication: When this erratum occurs there may be multiple PMIs observed when
IA32_FIXED_CTR0 overflows
Workaround: Disable the FREEZE_PERFMON_ON_PMI feature in IA32_DEBUGCTL MSR (1D9H) bit
[12].
Status: For the steppings affected, see the Summary Tables of Changes.
AAU67. VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct
Operand Size
Problem: When a VM exit occurs due to a LIDT, LGDT, SIDT, or SGDT instruction with a 32-bit
operand, bit 11 of the VM-exit instruction information field should be set to 1. Due to
this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).
Implication: Virtual-machine monitors cannot rely on bit 11 of the VM-exit instruction information
field to determine the operand size of the instruction causing the VM exit.
Workaround: Virtual Machine Monitor software may decode the instruction to determine operand
size.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU68. Performance Monitoring Events STORE_BLOCKS.NOT_STA and
STORE_BLOCKS.STA May Not Count Events Correctly
Problem: Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA
should only increment the count when a load is blocked by a store. Due to this erratum,
the count will be incremented whenever a load hits a store, whether it is blocked or can
forward. In addition this event does not count for specific threads correctly.
Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events
STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA may indicate a higher occurrence
of loads blocked by stores than have actually occurred. If Intel Hyper-Threading
Technology is enabled, the counts of loads blocked by stores may be unpredictable and
they could be higher or lower than the correct count.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
39
Specification Update
AAU69. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based
Sampling), overflow of the counter results in storage of a PEBS record in the PEBS
buffer. The information in the PEBS record represents the state of the next instruction
to be executed following the counter overflow. Due to this erratum, if the counter
overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is
delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record being
delayed by one instruction following execution of MOV SS or STI. The state information
in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU70. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts
transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if
only a small number of MMX instructions (including EMMS) are executed immediately
after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially-available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU71. INVLPG Following INVEPT or INVVPID May Fail to Flush All
Translations for a Large Page
Problem: This erratum applies if the address of the memory operand of an INVEPT or INVVPID
instruction resides on a page larger than 4KBytes and either (1) that page includes the
low 1 MBytes of physical memory; or (2) the physical address of the memory operand
matches an MTRR that covers less than 4 MBytes. A subsequent execution of INVLPG
that targets the large page and that occurs before the next VM-entry instruction may
fail to flush all TLB entries for the page. Such entries may persist in the TLB until the
next VM-entry instruction.
Implication: Accesses to the large page between INVLPG and the next VM-entry instruction may
incorrectly use translations that are inconsistent with the in-memory page tables.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
40
Specification Update
AAU72. Logical Processor May Use Incorrect VPID after VM Entry That Returns
From SMM
Problem: A logical processor in VMX root operation should use VPID 0000H. Due to this erratum,
a logical processor may instead use VPID 1FB3H if VMX root operation was entered
using a VM entry that returns from SMM.
Implication: After a VM entry that sets the "enable VPID" VM-execution control and that establishes
VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in
VMX root operation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU73. The Memory Controller May Hang Due to Uncorrectable ECC Errors or
Parity Errors Occurring on Both Channels in Mirror Channel Mode
Problem: If an uncorrectable ECC or parity error occurs on the mirrored channel before an
uncorrectable ECC or parity error on the other channel can be resolved, the Memory
Controller may hang without an uncorrectable ECC or parity error being logged.
Implication: The processor may hang and not report the error when uncorrectable ECC or parity
errors occur in close proximity on both channels in a mirrored channel pair. No
uncorrectable ECC or parity error will be logged in the machine check banks.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU74. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost
Technology Core Ratio Multipliers for Non-Existent Core
Configurations
Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel
Turbo Boost Technology potential of the processor. On some processors, a non-zero
Intel Turbo Boost Technology value will be returned for non-existent core
configurations.
Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel
Turbo Boost Technology processor capabilities may report erroneous results.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU75. Internal Parity Error May Be Incorrectly Signaled during C6 Exit
Problem: In a complex set of internal conditions an internal parity error may occur during a Core
C6 exit.
Implication: Due to this erratum, an uncorrected error may be reported and a machine check
exception may be triggered.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
41
Specification Update
AAU76. PMIs during Core C6 Transitions May Cause the System to Hang
Problem: If a performance monitoring counter overflows and causes a PMI (Performance
Monitoring Interrupt) at the same time that the core enters C6, then this may cause
the system to hang.
Implication: Due to this erratum, the processor may hang when a PMI coincides with core C6 entry.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU77. 2MB Page Split Lock Accesses Combined With Complex Internal
Events May Cause Unpredictable System Behavior
Problem: A 2MB Page Split Lock (a locked access that spans two 2MB large pages) coincident
with additional requests that have particular address relationships in combination with
a timing sensitive sequence of complex internal conditions may cause unpredictable
system behavior.
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU78. If the APIC timer Divide Configuration Register (Offset 03E0H) is
written at the same time that the APIC timer Current Count Register
(Offset 0390H) reads 1H, it is possible that the APIC timer will deliver
two interrupts.
Problem: If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same
time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible
that the APIC timer will deliver two interrupts.
Implication: Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer
event.
Workaround: Software should reprogram the Divide Configuration Register only when the APIC timer
interrupt is disarmed.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU79. TXT.PUBLIC.KEY is Not Reliable
Problem: On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the
TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to FED3_041FH) is not
reliable.
Implication: Due to this erratum, the TXT.PUBLIC.KEY value should not be relied on or used for
retrieving the hash of the TXT public key for the platform.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
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Specification Update
AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides
With Interrupt Acknowledge Cycle From the Preceding Interrupt
Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External
Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External
Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B
Mode External Interrupt request. This occurs when both the new External Interrupt and
Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the
same time.
Implication: to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will
subsequently be ignored.
Workaround: Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU82. The APIC Timer Current Count Register May Prematurely Read 0x0
While the Timer is Still Running
Problem: The APIC Timer Current Counter Register may prematurely read 0x00000000 while the
timer is still running. This problem occurs when a core frequency or C-state transition
occurs while the APIC timer countdown is in progress.
Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer
countdown is complete when it is actually still running. This erratum does not affect the
delivery of the timer interrupt.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU83. Secondary PCIe Port May Not Train After A Warm Reset
Problem: In a dual PCIe port configuration, the secondary PCIe port may not train after a warm
reset.
Implication: The second PCIe port and therefore any device connected to the PCIe bus instantiated
by that PCIe port may not be functional after a warm reset. Intel has not observed this
erratum with any commercially available system.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
43
Specification Update
AAU84. The PECI Bus May Be Tri-stated after System Reset
Problem: During power-up, the processor may improperly assert the PECI (Platform Environment
Control Interface) pin. This condition is cleared as soon as Bus Clock starts toggling.
However, if the PECI host (also referred to as the master or originator) incorrectly
determines this asserted state as another PECI host initiating a transaction, it may
release control of the bus resulting in a permanent tri-state condition.
Implication: Due to this erratum, the PECI host may incorrectly determine that it is not the bus
master and consequently PECI commands initiated by the PECI software layer may
receive incorrect/invalid responses.
Workaround: To workaround this erratum the PECI host should pull the PECI bus low to initiate a
PECI transaction.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU85. The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU86. Processor Hangs on Package C6 State Exit
Problem: An internal timing condition in the processor power management logic will result in
processor hangs upon a Package C6 state exit.
Implication: Due to this erratum, the processor will hang during Package C6 state exit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU87. A Synchronous SMI May be Delayed
Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI
generating I/O Write instruction and should be handled prior to the next instruction
executing. Due to this erratum, the processor may not observe the synchronous SMI
prior to execution of the next instruction.
Implication: Due to this erratum, instructions after the I/O Write instruction, which triggered the
SMI, may be allowed to execute before the SMI handler. Delayed delivery of the SMI
may make it difficult for an SMI Handler to determine the source of the SMI. Software
that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not
function as expected.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
44
Specification Update
AAU88. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an 80-
bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory
access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the
value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit
FP load around a 4-Gbyte boundary in this way is not a normal programming practice.
Intel has not observed this erratum with any commercially available software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run code
accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses
are wrapped around a 4-Gbyte boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU89. PCI Express x16 Port Links May Fail to Dynamically Switch From
5.0GT/s to 2.5GT/s
Problem: If an endpoint device initiates a PCI Express speed change from 5.0 GT/s to 2.5 GT/s,
the link may incorrectly go into Recovery.Idle rather than the expected Recovery.Speed
state. This may cause the link to lose sync, eventually resulting in a link down. The link
will recover and re-train to the L0 state, however any outstanding packets queued
during the speed change may be lost.
Implication: Due to this erratum, the link may lose sync resulting in link down with queued packet
being lost. No known failures have been observed on systems using production PCI
Express graphics cards. This erratum has only been observed in a synthetic test
environment.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU90. PCI Express Cards May Not Train to x16 Link Width
Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;
Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8,
even though the processor may actually be capable of supporting the full x16 width.
Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB
(Compliance Load Board) Cards used during PCI Express Compliance mode testing may
only train to x8 link width.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum
Status: For the steppings affected, see the Summary Tables of Changes.
AAU91. Unexpected Graphics VID Transition During Warm Reset May Cause
the System to Hang
Problem: During a warm reset to the processor, the graphics VID (Voltage ID) may transition to
an unexpected value that may cause the voltage regulator to shut off.
Implication: The processor may hang during integrated graphics initialization. Cold boots and
platforms using discrete graphics are not affected by this issue.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
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Status: For the steppings affected, see the Summary Tables of Changes.
Status:
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Specification Update
Specification Changes
The Specification Changes listed in this section apply to the following documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
There are no new Specification Changes in this Specification Update revision.
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Specification Clarifications
The Specification Clarifications listed in this section may apply to the following
documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
There are no new Specification Changes in this Specification Update revision.
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Specification Update
Documentation Changes
The Documentation Changes listed in this section apply to the following documents:
• Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volumes 1 and 2
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic
Architecture
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:
Instruction Set Reference Manual A-M
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:
Instruction Set Reference Manual N-Z
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:
System Programming Guide
• Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:
System Programming Guide
All Documentation Changes will be incorporated into a future version of the appropriate
Processor documentation.
Note: Documentation changes for Intel® 64 and IA-32 Architecture Software
Developer's Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate
document, Intel® 64 and IA-32 Architecture Software Developer's Manual
Documentation Changes. Follow the link below to become familiar with this file.
http://developer.intel.com/products/processor/manuals/index.htm
AAU1. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet, Volume 2 to add
PEG_TC—PCI Express Completion Timeout Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2 will be updated to include the PEG_TC—PCI
Express Completion Timeout Register in Section 2.11.7 as shown in the table below in
red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet - Volume 2
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Specification Update
2.11.7 PEG_TC—PCI Express Completion Timeout Register
This register reports PCI Express configuration control of PCI Express Completion
Timeout related parameters that are not required by the PCI Express spec.
AAU2. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet, Volume 2 to add
PEG_TC—PCI Express Completion Timeout to add SSKPD—Sticky
Scratchpad Data Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2 will be updated to include the SSKPD—Sticky
Scratchpad Data Register in Section 2.8.56 as shown in the table below in red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet, Volume 2
B/D/F/Type: 0/1/0/MMR
Address Offset: 204h
Reset Value: 0000_0C00h
Access: RW
Bit Attr Reset
Value Description
31:12 RW 0000_0h Reserved: (RSVD).
11:12 RW 11b
PCI Express Completion Timeout (PEG_TC)
Determines the number of milliseconds the Transaction Layer will wait to
receive an expected completion. To avoid hang conditions, the Transaction
Layer will generate a dummy completion to the requestor if it does not
receive the completion within this time period.
00: Disable
01: Reserved
10: Reserved
11: 48 ms - for normal operation(default)
9:0 RW 0_0000_0
000b
Reserved: (RSVD).
50
Specification Update
2.8.56 SSKPD—Sticky Scratchpad Data Register
This register holds 64 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
AAU3. Update to Intel® Core™ i5-600, i3-500 Desktop Processor Series and
Intel® Pentium® Processor G6950 Datasheet - Volume 2 to add
MCSAMPML—Memory Configuration, System Address Map and Preallocated
Memory Lock Register
Issue: The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium®
Processor G6950 Datasheet - Volume 2will be updated to include the
MCSAMPML—Memory Configuration, System Address Map and Pre-allocated Memory
Lock Register in Section 2.7.28 as shown in the table below in red text.
Affected Docs:Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor
G6950 Datasheet - Volume 2
2.7.28 MCSAMPML—Memory Configuration, System Address Map
and Pre-allocated Memory Lock Register
B/D/F/Type: 0/0/0/PCI
Address Offset: F4h
Reset Value: 00h
Access:
Bit Attr Reset
Value Description
7:5 RW-O 000b Reserved(RSDV)
4 RW-L 0 Reserved(RSDV)
3 RW-L-K 0
Lock Mode (LOCKMODE)
LOCKMODE and ME_SM_LOCK (bit 0) must always be programmed to the
same value. See bit 0 for description details.
0 = Registers are not locked
1 = Registers are locked.
2 RW-L 0 Reserved(RSDV)
1 RO 0 Reserved(RSDV)
0 RW-L-K 0
ME Stolen Memory Lock (ME_SM_LOCK)
When ME_SM_LOCK is set to 1 then all registers related to MCH configuration
become read only. BIOS will initialize config bits related to MCH configuration
and then use ME_SM_lock to "lock down" the MCH configuration in the future
so that no application software (or BIOS itself) can violate the integrity of
DRAM - including ME stolen memory space.
If BIOS writes this bit to '1` then bit 3 "LOCKMODE" bit must also be written
to '1` to ensure proper register lockdown.
If BIOS writes this bit to '0` then bit 3 "LOCKMODE" bit must also be written
to '0`.
This bit and LOCKMODE bit 3 should never be programmed differently.
PCI device 0 and MCHBAR registers affected by this bit are detailed within
the descriptions of the affected registers.
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PERTEMUAN 3

Unit Pengolah Pusat (UPP) (bahasa Inggris: CPU, singkatan dari Central Processing Unit), merujuk kepada perangkat keras komputer yang memahami dan melaksanakan perintah dan data dari perangkat lunak. Istilah lain, prosesor (pengolah data), sering digunakan untuk menyebut CPU. Adapun mikroprosesor adalah CPU yang diproduksi dalam sirkuit terpadu, seringkali dalam sebuah paket sirkuit terpadu-tunggal. Sejak pertengahan tahun 1970-an, mikroprosesor sirkuit terpadu-tunggal ini telah umum digunakan dan menjadi aspek penting dalam penerapan CPU.
Pin mikroprosesor Intel 80486DX2.
Daftar isi
[sembunyikan]

* 1 Komponen CPU
* 2 Cara Kerja CPU
o 2.1 Fungsi CPU
o 2.2 Percabangan instruksi
o 2.3 Bilangan yang dapat ditangani
* 3 Referensi
* 4 Pranala luar
o 4.1 Perancang CPU
o 4.2 Informasi lain

[sunting] Komponen CPU
Diagram blok sederhana sebuah CPU.

Komponen CPU terbagi menjadi beberapa macam, yaitu sebagai berikut.

* Unit kontrol yang mampu mengatur jalannya program. Komponen ini sudah pasti terdapat dalam semua CPU.CPU bertugas mengontrol komputer sehingga terjadi sinkronisasi kerja antar komponen dalam menjalankan fungsi-fungsi operasinya. termasuk dalam tanggung jawab unit kontrol adalah mengambil intruksi-intruksi dari memori utama dan menentukan jenis instruksi tersebut. Bila ada instruksi untuk perhitungan aritmatika atau perbandingan logika, maka unit kendali akan mengirim instruksi tersebut ke ALU. Hasil dari pengolahan data dibawa oleh unit kendali ke memori utama lagi untuk disimpan, dan pada saatnya akan disajikan ke alat output. Dengan demikian tugas dari unit kendali ini adalah:

• Mengatur dan mengendalikan alat-alat input dan output. • Mengambil instruksi-instruksi dari memori utama. • Mengambil data dari memori utama (jika diperlukan) untuk diproses. • Mengirim instruksi ke ALU bila ada perhitungan aritmatika atau perbandingan logika serta mengawasi kerja dari ALU. • Menyimpan hasil proses ke memori utama.

* Register merupakan alat penyimpanan kecil yang mempunyai kecepatan akses cukup tinggi, yang digunakan untuk menyimpan data dan/atau instruksi yang sedang diproses. Memori ini bersifat sementara, biasanya di gunakan untuk menyimpan data saat di olah ataupun data untuk pengolahan selanjutnya. Secara analogi, register ini dapat diibaratkan sebagai ingatan di otak bila kita melakukan pengolahan data secara manual, sehingga otak dapat diibaratkan sebagai CPU, yang berisi ingatan-ingatan, satuan kendali yang mengatur seluruh kegiatan tubuh dan mempunyai tempat untuk melakukan perhitungan dan perbandingan logika.
* ALU unit yang bertugas untuk melakukan operasi aritmetika dan operasi logika berdasar instruksi yang ditentukan. ALU sering di sebut mesin bahasa karena bagian ini ALU terdiri dari dua bagian, yaitu unit arithmetika dan unit logika boolean yang masing-masing memiliki spesifikasi tugas tersendiri. Tugas utama dari ALU adalah melakukan semua perhitungan aritmatika (matematika) yang terjadi sesuai dengan instruksi program. ALU melakukan semua operasi aritmatika dengan dasar penjumlahan sehingga sirkuit elektronik yang digunakan disebut adder.

Tugas lain dari ALU adalah melakukan keputusan dari suatu operasi logika sesuai dengan instruksi program. Operasi logika meliputi perbandingan dua operand dengan menggunakan operator logika tertentu, yaitu sama dengan (=), tidak sama dengan (¹ ), kurang dari (<), kurang atau sama dengan (£ ), lebih besar dari (>), dan lebih besar atau sama dengan (³ ).

* CPU Interconnections adalah sistem koneksi dan bus yang menghubungkan komponen internal CPU, yaitu ALU, unit kontrol dan register-register dan juga dengan bus-bus eksternal CPU yang menghubungkan dengan sistem lainnya, seperti memori utama, piranti masukan /keluaran.

[sunting] Cara Kerja CPU

Saat data dan/atau instruksi dimasukkan ke processing-devices, pertama sekali diletakkan di RAM (melalui Input-storage); apabila berbentuk instruksi ditampung oleh Control Unit di Program-storage, namun apabila berbentuk data ditampung di Working-storage). Jika register siap untuk menerima pengerjaan eksekusi, maka Control Unit akan mengambil instruksi dari Program-storage untuk ditampungkan ke Instruction Register, sedangkan alamat memori yang berisikan instruksi tersebut ditampung di Program Counter. Sedangkan data diambil oleh Control Unit dari Working-storage untuk ditampung di General-purpose register (dalam hal ini di Operand-register). Jika berdasar instruksi pengerjaan yang dilakukan adalah arithmatika dan logika, maka ALU akan mengambil alih operasi untuk mengerjakan berdasar instruksi yang ditetapkan. Hasilnya ditampung di Accumulator. Apabila hasil pengolahan telah selesai, maka Control Unit akan mengambil hasil pengolahan di Accumulator untuk ditampung kembali ke Working-storage. Jika pengerjaan keseluruhan telah selesai, maka Control Unit akan menjemput hasil pengolahan dari Working-storage untuk ditampung ke Output-storage. Lalu selanjutnya dari Output-storage, hasil pengolahan akan ditampilkan ke output-devices.
[sunting] Fungsi CPU

CPU berfungsi seperti kalkulator, hanya saja CPU jauh lebih kuat daya pemrosesannya. Fungsi utama dari CPU adalah melakukan operasi aritmatika dan logika terhadap data yang diambil dari memori atau dari informasi yang dimasukkan melalui beberapa perangkat keras, seperti papan ketik, pemindai, tuas kontrol, maupun tetikus. CPU dikontrol menggunakan sekumpulan instruksi perangkat lunak komputer. Perangkat lunak tersebut dapat dijalankan oleh CPU dengan membacanya dari media penyimpan, seperti cakram keras, disket, cakram padat, maupun pita perekam. Instruksi-instruksi tersebut kemudian disimpan terlebih dahulu pada memori fisik (RAM), yang mana setiap instruksi akan diberi alamat unik yang disebut alamat memori. Selanjutnya, CPU dapat mengakses data-data pada RAM dengan menentukan alamat data yang dikehendaki.

Saat sebuah program dieksekusi, data mengalir dari RAM ke sebuah unit yang disebut dengan bus, yang menghubungkan antara CPU dengan RAM. Data kemudian didekode dengan menggunakan unit proses yang disebut sebagai pendekoder instruksi yang sanggup menerjemahkan instruksi. Data kemudian berjalan ke unit aritmatika dan logika (ALU) yang melakukan kalkulasi dan perbandingan. Data bisa jadi disimpan sementara oleh ALU dalam sebuah lokasi memori yang disebut dengan register supaya dapat diambil kembali dengan cepat untuk diolah. ALU dapat melakukan operasi-operasi tertentu, meliputi penjumlahan, perkalian, pengurangan, pengujian kondisi terhadap data dalam register, hingga mengirimkan hasil pemrosesannya kembali ke memori fisik, media penyimpan, atau register apabila akan mengolah hasil pemrosesan lagi. Selama proses ini terjadi, sebuah unit dalam CPU yang disebut dengan penghitung program akan memantau instruksi yang sukses dijalankan supaya instruksi tersebut dapat dieksekusi dengan urutan yang benar dan sesuai.
[sunting] Percabangan instruksi

Pemrosesan instruksi dalam CPU dibagi atas dua tahap, Tahap-I disebut Instruction Fetch, sedangkan Tahap-II disebut Instruction Execute. Tahap-I berisikan pemrosesan CPU dimana Control Unit mengambil data dan/atau instruksi dari main-memory ke register, sedangkan Tahap-II berisikan pemrosesan CPU dimana Control Unit menghantarkan data dan/atau instruksi dari register ke main-memory untuk ditampung di RAM, setelah Instruction Fetch dilakukan. Waktu pada tahap-I ditambah dengan waktu pada tahap-II disebut waktu siklus mesin (machine cycles time).

Penghitung program dalam CPU umumnya bergerak secara berurutan. Walaupun demikian, beberapa instruksi dalam CPU, yang disebut dengan instruksi lompatan, mengizinkan CPU mengakses instruksi yang terletak bukan pada urutannya. Hal ini disebut juga percabangan instruksi (branching instruction). Cabang-cabang instruksi tersebut dapat berupa cabang yang bersifat kondisional (memiliki syarat tertentu) atau non-kondisional. Sebuah cabang yang bersifat non-kondisional selalu berpindah ke sebuah instruksi baru yang berada di luar aliran instruksi, sementara sebuah cabang yang bersifat kondisional akan menguji terlebih dahulu hasil dari operasi sebelumnya untuk melihat apakah cabang instruksi tersebut akan dieksekusi atau tidak. Data yang diuji untuk percabangan instruksi disimpan pada lokasi yang disebut dengan flag.
[sunting] Bilangan yang dapat ditangani

Kebanyakan CPU dapat menangani dua jenis bilangan, yaitu fixed-point dan floating-point. Bilangan fixed-point memiliki nilai digit spesifik pada salah satu titik desimalnya. Hal ini memang membatasi jangkauan nilai yang mungkin untuk angka-angka tersebut, tetapi hal ini justru dapat dihitung oleh CPU secara lebih cepat. Sementara itu, bilangan floating-point merupakan bilangan yang diekspresikan dalam notasi ilmiah, di mana sebuah angka direpresentasikan sebagai angka desimal yang dikalikan dengan pangkat 10 (seperti 3,14 x 1057). Notasi ilmiah seperti ini merupakan cara yang singkat untuk mengekspresikan bilangan yang sangat besar atau bilangan yang sangat kecil, dan juga mengizinkan jangkauan nilai yang sangat jauh sebelum dan sesudah titik desimalnya. Bilangan ini umumnya digunakan dalam merepresentasikan grafik dan kerja ilmiah, tetapi proses aritmatika terhadap bilangan floating-point jauh lebih rumit dan dapat diselesaikan dalam waktu yang lebih lama oleh CPU karena mungkin dapat menggunakan beberapa siklus detak CPU. Beberapa komputer menggunakan sebuah prosesor sendiri untuk menghitung bilangan floating-point yang disebut dengan FPU (disebut juga math co-processor) yang dapat bekerja secara paralel dengan CPU untuk mempercepat penghitungan bilangan floating-point. FPU saat ini menjadi standar dalam banyak komputer karena kebanyakan aplikasi saat ini banyak beroperasi menggunakan bilangan floating-point.

PERTEMUAN 4

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TEKNIK DIGITAL
IV. GERBANG-GERBANG LOGIKA
Anhar, ST, MT.
Anhar.net63.net
OUTLINE
􀁼 Pengantar
􀁼 Logika positif dan negatif
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􀁼 Tabel kebenaran
􀁼 Gerbang-gerbang logika
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PENGANTAR
􀁼 Gerbang-gerbang logika adlh rangkaian elektronika
yg digunakan utk mengaplikasikan persamaan logika
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dasar, spt pers Boolean.
􀁼 Gerbang logika merupakan blok yg paling dasar dr
logika kombinasional.
􀁼 Ada 3 gerbang logika dasar :
􀁹 Gerbang OR
􀁹 Gerbang AND
􀁹 Gerbang NOT
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􀁼 Gerbang yg diturunkan dr gerbang diatas adlh :
􀁹 Gerbang NAND
􀁹 Gerbang NOR
􀁹 Gerbang EX-OR
􀁹 Gerbang EX-NOR 3
LOGIKA POSITIF DAN NEGATIF
􀁼 Bilangan biner dinyatakan dng 2 keadaan, logika
0 dan logika 1.
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􀁼 Logika ini dlm sistem peralatan digital mengacu
pd 2 level tegangan/arus.
􀁼 Bila lebih banyak positif dr 2 teg./arus 􀖥1
􀁼 Bila lebih sedikit positif dr 2 teg./arus 􀖥0, atau
sebaliknya.
Anhar, ST, MT
􀁼 Contoh :
􀁹 Bila 2 teg berlevel 0 V dan +5 V, maka dlm sistem
logika positif, 0 V = logika 0, dan +5 V = logika 1.
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TABEL KEBENARAN
􀁼 Merupakan suatu tabel yg mencantumkan
semua kemungkinan input biner dan output yg
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berhubungan dr sistem logika.
􀁼 Bila variabel input 1, maka ada 2 kemungkinan
input, 0 atau 1.
􀁼 Bila variabel input 2, maka ada 4 kemungkinan
input, dst.
Bil d i t bi k t b l k b
Anhar, ST, MT
􀁼 Bila ada n input biner, maka tabel kebenarannya
akan memiliki 2n kombinasi input, atau 2n baris.
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􀁼 Tabel kebenaran utk 2 dan 3 input.
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GERBANG LOGIKA
1. GERBANG OR
􀁼 Membentuk operasi OR dr 2 atau 3 gerbang
masukan.
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􀁼 Dlm persamaan logika : Y = A + B
􀁼 Gerbang OR 2 masukan :
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􀁼 Gerbang OR 3 dan 4 masukan :
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􀁼 Contoh 1 :
􀁼 Bagaimana cara mengaplikasikan gerbang OR 4
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masukan dng menggunakan gerbang OR
2masukan?
􀁼 Penyelesaian :
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􀁼 Contoh 2 :
􀁼 Gambarkan bentuk pulsa keluaran pd gerbang
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OR utk pulsa masukan spt gbr berikut ini.
Anhar, ST, MT
􀁼 Penyelesaian :
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GERBANG LOGIKA
2. GERBANG AND
􀁼 Output gerbang AND hanya bernilai 1 bila kedua
masukan 1, sedangkan lainnya 0.
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􀁼 Dlm pers. Logika : Y = A. B
􀁼 Gerbang AND 2 masukan :
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􀁼 Gerbang AND 3 dan 4 masukan :
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􀁼 Contoh 3 :
􀁼 Susunlah gerbang AND 4 masukan dng
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menggunakan gerbang AND 2 masukan.
􀁼 Penyelesaian :
Anhar, ST, MT
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GERBANG LOGIKA
3. GERBANG NOT
􀁼 Merupakan rangkaian logika 1 output, dimana
outputnya selalu merupakan kebalikan dr input.
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􀁼 Dlm persamaan logika, bila inputnya X maka :
􀁼 Simbol rangkaian dan tabel kebenaran :
Anhar, ST, MT
Y = X atau Y = X '
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􀁼 Contoh 4 :
􀁼 Untuk rangkaian logika berikut, tentukan pulsa
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keluarannya.
Anhar, ST, MT
􀁼 Penyelesaian :
􀁼 Utk gbr (a), outputnya akan selalu 1 krn kedua inputnya
tdk bisa sama2 0.
􀁼 Utk gbr (b), outputnya akan selalu 0 krn kedua inputnya
tdk bisa sama2 1. 15
GERBANG LOGIKA
4. GERBANG EXCLUSIVE-OR
􀁼 Gerbang Ex-OR bernilai 1 bila inputnya tdk
sama, dan bernilai 0 bila inputnya sama.
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􀁼 Dlm pers logika : Y = A 􀙒B =
􀁼 Simbol rangk utk 2 masukan serta tabel
kebenaran utk 2 dan 3 masukan.
Anhar, ST, MT
AB + AB
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􀁼 Contoh 5 :
􀁼 Gambarkan implementasi gerbang Ex OR 3 dan
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Ex-4 masukan dng menggunakan Ex-OR 2
masukan.
􀁼 Penyelesaian :
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GERBANG LOGIKA
5. GERBANG NAND
􀁼 Menyatakan NOT AND
􀁼 Tabel kebenarannya merupakan kebalikan dari
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AND
􀁼 Persamaan boolean :
􀁼 Diagram rangk dan tabel kebenaran
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GERBANG LOGIKA
5. GERBANG NOR
􀁼 Menyatakan NOT OR
􀁼 Tabel kebenarannya merupakan kebalikan dari OR
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􀁼 Persamaan boolean :
􀁼 Diagram rangk dan tabel kebenaran
Anhar, ST, MT
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GERBANG LOGIKA
5. GERBANG EX-NOR
􀁼 Menyatakan NOT OR
􀁼 Tabel kebenarannya merupakan kebalikan dari
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Ex-OR
􀁼 Persamaan boolean :
􀁼 Diagram rangk dan tabel kebenaran
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􀁼 Contoh 6 :
􀁼 Perlihatkan cara menyusun gerbang logika utk
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implementasi berikut ini :
􀁹 Gerbang NAND 4 input menggunakan gerbang AND 2 input
dan 1 inverter.
􀁹 Gerbang NAND 3 input menggunakan gerbang NAND 2 input
􀁹 Rangkaian NOT menggunakan 2 input gerbang NAND
􀁹 Rangkaian NOT menggunakan 2 input gerbang NOR
R ki NOT k 2 i t b E OR
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􀁹 Rangkaian menggunakan input gerbang Ex-21
􀁼 Penyelesaian :
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GERBANG LOGIKA
6. GERBANG PENGHALANG
􀁼 Sebagai pembalik masukan sebelum melewati
gerbang
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􀁼 Contoh diagram rangkaian 4 input dng salah
satu gerbang penghalang dan tabel
kebenarannya.
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􀁼 Contoh :
􀁼 Lihat diagram rangkaian (a) dibawah ini Bila
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ini. gambar (b) merupakan pulsa masukannya,
tentukan pulsa keluarannya.
Anhar, ST, MT
􀁼 Penyelesaian :
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LATIHAN
1. Buat tabel kebenaran utk diagram rangkaian
spt berikut ini.
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2. Gambarkan implementasi logika Inverter
dengan menggunakan (i) NAND 2 input, (ii)
NOR 2 input (iii) EX-OR 2 input (iv) EX-NOR
Anhar, ST, MT
input, input, 2 input.
3. Rancanglah gerbang NAND 8 masukan dng
menggunakan gerbang AND 2 input dan
gerbang NAND 2 input. 25